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| * Fix PM disable depth imbalance in probeMark Brown2022-09-273-2/+6
| |\ | | | | | | | | | | | | | | | | | | | | | Merge series from Zhang Qilong <zhangqilong3@huawei.com>: The pm_runtime_enable will increase power disable depth. Thus a pairing decrement is needed when error returns to keep it balanced. This series of patches fixed it in spi probe.
| | * spi/omap100k:Fix PM disable depth imbalance in omap1_spi100k_probeZhang Qilong2022-09-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pm_runtime_enable will increase power disable depth. Thus a pairing decrement is needed on the error handling path to keep it balanced according to context. Fixes:db91841b58f9a ("spi/omap100k: Convert to runtime PM") Signed-off-by: Zhang Qilong <zhangqilong3@huawei.com> Link: https://lore.kernel.org/r/20220924121310.78331-4-zhangqilong3@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
| | * spi: dw: Fix PM disable depth imbalance in dw_spi_bt1_probeZhang Qilong2022-09-261-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pm_runtime_enable will increase power disable depth. Thus a pairing decrement is needed on the error handling path to keep it balanced according to context. Fixes:abf00907538e2 ("spi: dw: Add Baikal-T1 SPI Controller glue driver") Signed-off-by: Zhang Qilong <zhangqilong3@huawei.com> Link: https://lore.kernel.org/r/20220924121310.78331-3-zhangqilong3@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
| | * spi: cadence-quadspi: Fix PM disable depth imbalance in cqspi_probeZhang Qilong2022-09-261-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pm_runtime_enable will increase power disable depth. Thus a pairing decrement is needed on the error handling path to keep it balanced according to context. Fixes:73d5fe0462702 ("spi: cadence-quadspi: Remove spi_master_put() in probe failure path") Signed-off-by: Zhang Qilong <zhangqilong3@huawei.com> Link: https://lore.kernel.org/r/20220924121310.78331-2-zhangqilong3@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi: spi-fsl-qspi: Use devm_platform_ioremap_resource_byname()Yang Yingliang2022-09-261-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the devm_platform_ioremap_resource_byname() helper instead of calling platform_get_resource_byname() and devm_ioremap_resource() separately. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20220924131854.964923-3-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi: spi-fsl-lpspi: Use devm_platform_get_and_ioremap_resource()Yang Yingliang2022-09-261-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use the devm_platform_get_and_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20220924131854.964923-2-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi: spi-fsl-dspi: Use devm_platform_get_and_ioremap_resource()Yang Yingliang2022-09-261-2/+1
| |/ | | | | | | | | | | | | | | | | Use the devm_platform_get_and_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20220924131854.964923-1-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: s3c24xx: Switch to use devm_spi_alloc_master()Yang Yingliang2022-09-231-16/+8
| | | | | | | | | | | | | | | | | | Switch to use devm_spi_alloc_master() to simpify error path. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220920142216.3002291-1-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: xilinx: Switch to use devm_spi_alloc_master()Yang Yingliang2022-09-231-14/+6
| | | | | | | | | | | | | | | | | | Switch to use devm_spi_alloc_master() to simpify error path. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Lukas Wunner <lukas@wunner.de> Link: https://lore.kernel.org/r/20220920114615.2681751-1-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: img-spfi: using pm_runtime_resume_and_get instead of pm_runtime_get_syncZhang Qilong2022-09-231-4/+2
| | | | | | | | | | | | | | | | | | Using the newest pm_runtime_resume_and_get is more appropriate for simplifing code here. Signed-off-by: Zhang Qilong <zhangqilong3@huawei.com> Link: https://lore.kernel.org/r/20220922150232.115843-1-zhangqilong3@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: aspeed: Remove redundant dev_err callShang XiaoJing2022-09-231-3/+1
| | | | | | | | | | | | | | | | | | | | devm_ioremap_resource() prints error message in itself. Remove the dev_err call to avoid redundant error message. Signed-off-by: Shang XiaoJing <shangxiaojing@huawei.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Link: https://lore.kernel.org/r/20220923101632.19170-1-shangxiaojing@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: spi-mpc52xx: switch to using gpiod APIDmitry Torokhov2022-09-231-19/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | This switches the driver to use gpiod API instead of legacy gpio API, which will brings us close to removing of_get_gpio() and other OF-specific old APIs. No functional change intended beyond some differences in error messages. Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/Yy07WbMAG4bPgYNd@google.com Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: cadence: Remove redundant dev_err callShang XiaoJing2022-09-231-3/+1
| | | | | | | | | | | | | | | | | | devm_ioremap_resource() prints error message in itself. Remove the dev_err call to avoid redundant error message. Signed-off-by: Shang XiaoJing <shangxiaojing@huawei.com> Link: https://lore.kernel.org/r/20220923101726.19420-1-shangxiaojing@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: xtensa-xtfpga: Switch to use devm_spi_alloc_master()Yang Yingliang2022-09-221-11/+5
| | | | | | | | | | | | | | | | | | | | Switch to use devm_spi_alloc_master() to simpify error path. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Tested-by: Max Filippov <jcmvbkbc@gmail.com> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Link: https://lore.kernel.org/r/20220920114448.2681053-1-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: meson-spicc: make symbol 'meson_spicc_pow2_clk_ops' staticWei Yongjun2022-09-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The sparse tool complains as follows: drivers/spi/spi-meson-spicc.c:570:22: warning: symbol 'meson_spicc_pow2_clk_ops' was not declared. Should it be static? This symbol is not used outside of spi-meson-spicc.c, so marks it static. Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20220922040807.1409540-1-weiyongjun@huaweicloud.com Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: omap2-mcspi: Fix probe so driver works againDan Carpenter2022-09-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | This condition was accidentally changed from "if (status < 0)" to "if (status)". The platform_get_irq() function returns non-zero positive values on success so, unfortunately, the driver could not be used. Change the condition back to how it was. Fixes: f4ca8c88c2c7 ("spi: omap2-mcspi: Switch to use dev_err_probe() helper") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/Yyq8Q/kd301wVzg8@kili Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: spi-loopback-test: Add test to trigger DMA/PIO mixingVincent Whitchurch2022-09-191-0/+27
| | | | | | | | | | | | | | | | | | | | Add a test where a small and a large transfer in a message hit the same cache line. This test currently fails on spi-s3c64xx on in DMA mode since it ends up mixing DMA and PIO without proper cache maintenance. Signed-off-by: Vincent Whitchurch <vincent.whitchurch@axis.com> Link: https://lore.kernel.org/r/20220916113951.228398-2-vincent.whitchurch@axis.com Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: omap2-mcspi: Switch to use dev_err_probe() helperYang Yingliang2022-09-191-4/+2
| | | | | | | | | | | | | | | | | | | | In the probe path, dev_err() can be replace with dev_err_probe() which will check if error code is -EPROBE_DEFER and prints the error name. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20220917122504.1896302-1-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: mpc52xx: Replace of_gpio_count() by gpiod_count()Andy Shevchenko2022-09-141-1/+2
| | | | | | | | | | | | | | | | | | As a preparation to unexport of_gpio_named_count(), convert the driver to use gpiod_count() instead. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220914153333.37701-1-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: fsl_spi: Convert to transfer_oneChristophe Leroy2022-09-141-114/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Let the core handle all the chipselect bakery and replace transfer_one_message() by transfer_one() and prepare_message(). At the time being, there is fsl_spi_cs_control() to handle chipselects. That function handles both GPIO and non-GPIO chipselects. The GPIO chipselects will now be handled by the core directly, so only handle non-GPIO chipselects and hook it to ->set_cs Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/753266abafe81722d86c3ddb8bac8ef1cb00fe8c.1660829841.git.christophe.leroy@csgroup.eu Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: meson-spicc: do not rely on busy flag in pow2 clk opsNeil Armstrong2022-09-081-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since [1], controller's busy flag isn't set anymore when the __spi_transfer_message_noqueue() is used instead of the __spi_pump_transfer_message() logic for spi_sync transfers. Since the pow2 clock ops were limited to only be available when a transfer is ongoing (between prepare_transfer_hardware and unprepare_transfer_hardware callbacks), the only way to track this down is to check for the controller cur_msg. [1] ae7d2346dc89 ("spi: Don't use the message queue if possible in spi_sync") Fixes: 09992025dacd ("spi: meson-spicc: add local pow2 clock ops to preserve rate between messages") Fixes: ae7d2346dc89 ("spi: Don't use the message queue if possible in spi_sync") Reported-by: Markus Schneider-Pargmann <msp@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Markus Schneider-Pargmann <msp@baylibre.com> Link: https://lore.kernel.org/r/20220908121803.919943-1-narmstrong@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: lpspi: Remove the unneeded result variableye xingchen2022-09-081-4/+1
| | | | | | | | | | | | | | | | | | | | Return the value pm_runtime_force_suspend() directly instead of storing it in another redundant variable. Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn> Link: https://lore.kernel.org/r/20220908010429.342875-1-ye.xingchen@zte.com.cn Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: Add capability to perform some transfer with chipselect offChristophe Leroy2022-09-071-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some components require a few clock cycles with chipselect off before or/and after the data transfer done with CS on. Typically IDT 801034 QUAD PCM CODEC datasheet states "Note *: CCLK should have one cycle before CS goes low, and two cycles after CS goes high". The cycles "before" are implicitely provided by all previous activity on the SPI bus. But the cycles "after" must be provided in order to terminate the SPI transfer. In order to use that kind of component, add a cs_off flag to spi_transfer struct. When this flag is set, the transfer is performed with chipselect off. This allows consummer to add a dummy transfer at the end of the transfer list which is performed with chipselect OFF, providing the required additional clock cycles. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/434165c46f06d802690208a11e7ea2500e8da4c7.1662558898.git.christophe.leroy@csgroup.eu Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: nxp-fspi: Do not dereference fwnode in struct deviceAndy Shevchenko2022-09-071-4/+4
| | | | | | | | | | | | | | | | | | | | In order to make the underneath API easier to change in the future, prevent users from dereferencing fwnode from struct device. Instead, use the specific dev_fwnode() API for that. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220906161048.39953-1-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: qup: add missing clk_disable_unprepare on error in ↵Xu Qiang2022-09-051-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | spi_qup_pm_resume_runtime() Add the missing clk_disable_unprepare() before return from spi_qup_pm_resume_runtime() in the error handling case. Fixes: dae1a7700b34 (“spi: qup: Handle clocks in pm_runtime suspend and resume”) Signed-off-by: Xu Qiang <xuqiang36@huawei.com> Link: https://lore.kernel.org/r/20220825065324.68446-2-xuqiang36@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: qup: add missing clk_disable_unprepare on error in spi_qup_resume()Xu Qiang2022-09-051-3/+14
| | | | | | | | | | | | | | | | | | | | Add the missing clk_disable_unprepare() before return from spi_qup_resume() in the error handling case. Fixes: 64ff247a978f (“spi: Add Qualcomm QUP SPI controller support”) Signed-off-by: Xu Qiang <xuqiang36@huawei.com> Link: https://lore.kernel.org/r/20220825065324.68446-1-xuqiang36@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: stm32-qspi: Refactor dual flash mode enable check in ->setup()Andy Shevchenko2022-08-311-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | gpiod_count() either returns positive number of the CS or negative error code. In the stm32_qspi_setup() we check that configuration has enough CS for the dual flash mode and SPI mode is not changing over the lines of the code. Taking all above into considertion, refactor dual flash mode enable check by dropping unneeded CS check and reusing local mode variable. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20220830182821.47919-2-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: stm32-qspi: Replace of_gpio_named_count() by gpiod_count()Andy Shevchenko2022-08-311-2/+2
| | | | | | | | | | | | | | | | | | | | As a preparation to unexport of_gpio_named_count(), convert the driver to use gpiod_count() instead. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20220830182821.47919-1-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: amd: Fix speed selectionShreeya Patel2022-08-301-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | If the current speed is equal to the requested speed by the device then return success. This patch fixes a bug introduced by the commit 3fe26121dc3a ("spi: amd: Configure device speed") which checks speed_hz instead of amd_spi->speed_hz. Fixes: 3fe26121dc3a ("spi: amd: Configure device speed") Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com> Link: https://lore.kernel.org/r/20220830093607.45484-1-shreeya.patel@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
| * spi: mt7621: Fix an erroneous message + clean-upsMark Brown2022-08-291-36/+6
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge series from Christophe JAILLET <christophe.jaillet@wanadoo.fr>: Patch 1 fixes an issue about an error code that is erroneously logged. Patch 2-4 are just clean-ups spotted while fixing it. Additional comments are added below --- in patches 2 and 3.
| | * spi: mt7621: Remove 'clk' from 'struct mt7621_spi'Christophe JAILLET2022-08-291-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | The 'clk' field in 'struct mt7621_spi' is useless, remove it. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/76ed0ef91479498b9a2d5ef539f80851cffdb4ea.1661599671.git.christophe.jaillet@wanadoo.fr Signed-off-by: Mark Brown <broonie@kernel.org>
| | * spi: mt7621: Use devm_spi_register_controller()Christophe JAILLET2022-08-291-15/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that clk_disable_unprepare(clk) is handled with a managed resource, we can use devm_spi_register_controller() and axe the .remove function. The order between spi_unregister_controller() and clk_disable_unprepare() is still the same. (see commit 46b5c4fb87ce ("spi: mt7621: Don't leak SPI master in probe error path") to see why it matters) Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Link: https://lore.kernel.org/r/b7698e198acc998d99e7e7c895a2910f14f89443.1661599671.git.christophe.jaillet@wanadoo.fr Signed-off-by: Mark Brown <broonie@kernel.org>
| | * spi: mt7621: Use the devm_clk_get_enabled() helper to simplify error handlingChristophe JAILLET2022-08-291-13/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The devm_clk_get_enabled() helper: - calls devm_clk_get() - calls clk_prepare_enable() and registers what is needed in order to call clk_disable_unprepare() when needed, as a managed resource. This helper is well suited for cases where the clock would be kept prepared or enabled for the whole lifetime of the driver. This simplifies the error handling a lot. The order between spi_unregister_controller() (in the remove function) and the clk_disable_unprepare() (now handle by a managed resource) is kept the same. (see commit 46b5c4fb87ce ("spi: mt7621: Don't leak SPI master in probe error path") to see why it matters) Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Link: https://lore.kernel.org/r/05a7fd22719008c8a905d6328aa9548ce40f2a7a.1661599671.git.christophe.jaillet@wanadoo.fr Signed-off-by: Mark Brown <broonie@kernel.org>
| | * spi: mt7621: Fix an error message in mt7621_spi_probe()Christophe JAILLET2022-08-291-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'status' is known to be 0 at this point. The expected error code is PTR_ERR(clk). Switch to dev_err_probe() in order to display the expected error code (in a human readable way). This also filters -EPROBE_DEFER cases, should it happen. Fixes: 1ab7f2a43558 ("staging: mt7621-spi: add mt7621 support") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Link: https://lore.kernel.org/r/928f3fb507d53ba0774df27cea0bbba4b055993b.1661599671.git.christophe.jaillet@wanadoo.fr Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi: add generic R-Car Gen4 and specific r8a779f0 supportMark Brown2022-08-291-0/+1
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | Merge series from Wolfram Sang <wsa+renesas@sang-engineering.com>: Here are the patches to enable MSIOF on R-Car S4-8. They also introduce generic Gen4 support and move V3U to Gen4 (which it really is).
| | * | spi: sh-msiof: add generic Gen4 bindingWolfram Sang2022-08-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No further changes in this generation discovered yet. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20220824094327.33685-3-wsa+renesas@sang-engineering.com Signed-off-by: Mark Brown <broonie@kernel.org>
| * | | spi: stm32-qspi: Fix pm_runtime management in stm32_qspi_transfer_one_message()Patrice Chotard2022-08-291-1/+7
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ctrl->auto_runtime_pm was wrongly set to true when adding transfer_one_message() callback. As explained in commit 6e6ccb3d4cdc ("spi: stm32-qspi: Add pm_runtime support") the expected behavior is to prevent runtime suspends between each transfer. Add needed pm_runtime API calls in stm32_qspi_transfer_one_message(). Fixes: a557fca630cc ("spi: stm32_qspi: Add transfer_one_message() spi callback") Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20220829123250.2170562-1-patrice.chotard@foss.st.com Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi: stm32-qspi: Fix stm32_qspi_transfer_one_message() error pathPatrice Chotard2022-08-281-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch a557fca630cc: "spi: stm32_qspi: Add transfer_one_message() spi callback" from Aug 23, 2022, leads to the following Smatch static checker warning: drivers/spi/spi-stm32-qspi.c:627 stm32_qspi_transfer_one_message() error: uninitialized symbol 'ret'.Fix the following Smatch static checker warning: Fixes: a557fca630cc ("spi: stm32_qspi: Add transfer_one_message() spi callback") Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20220826092031.1393430-1-patrice.chotard@foss.st.com Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi: amd: Configure device speedLucas Tanure2022-08-251-0/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Number of clock frequencies are supported by AMD controller which are mentioned in the amd_spi_freq structure table. Create mechanism to configure device clock frequency such that it is strictly less than the requested frequency. Give priority to the device transfer speed and in case it is not set then use the max clock speed supported by the device. Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Co-developed-by: Shreeya Patel <shreeya.patel@collabora.com> Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com> Link: https://lore.kernel.org/r/20220825143132.253224-1-shreeya.patel@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi: pxa2xx: Remove the unneeded result variableye xingchen2022-08-251-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Return the value clk_prepare_enable() directly instead of storing it in another redundant variable. Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn> Link: https://lore.kernel.org/r/20220825072828.229294-1-ye.xingchen@zte.com.cn Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi: stm32_qspi: use QSPI bus as 8 lines communication channelMark Brown2022-08-231-9/+109
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge series from patrice.chotard@foss.st.com <patrice.chotard@foss.st.com>: The goal of this series is to allow to use QSPI bus as a 8 lines communication channel for specific purpose. The QSPI block offers the possibility to communicate with 2 flashes in parrallel using the dual flash mode, 8 data lines are then used. Usage of cs-gpios populated and spi-tx-bus-width / spi-rx-bus-width both set to 8, is needed to enable dual flash mode. The addition of the legacy transfer_one_message() spi callback is also needed as currently the stm32-qspi driver only supports spi_controller_mem_ops API.
| | * | spi: stm32_qspi: Add transfer_one_message() spi callbackPatrice Chotard2022-08-231-9/+109
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add transfer_one_message() spi callback in order to use the QSPI interface as a communication channel using up to 8 qspi lines (QSPI configured in dual flash mode). To enable this mode, both spi-rx-bus-width and spi-tx-bus-width must be set to 8 and cs-qpios must be populated. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20220823075850.575043-3-patrice.chotard@foss.st.com Signed-off-by: Mark Brown <broonie@kernel.org>
| * | | spi: dw: Quite logging on deferred controller registrationSerge Semin2022-08-231-1/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's pretty possible to have the spi_register_controller() method returning -EPROBE_DEFER status in case, for instance, if the GPIOs used for the CS implementation aren't ready to be requested due to the corresponding platform devices still pending to be probed. Let's make sure the DW SSI driver won't print error message in that case by calling the dev_err_probe() function if the SPI-registration procedure exited with a non-zero status. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20220822181853.23063-1-Sergey.Semin@baikalelectronics.ru Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi: intel: 64k erase is supported from Canon Lake and beyondMika Westerberg2022-08-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The hardware sequencer in Intel Canon Lake and beyond supports also 64k erase command. The SPI-NOR core uses SFDP (Serial Flash Discovery Parameter) to figure out what the chip actually supports and only issues 64k erase if it is supported. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20220816125537.89389-1-mika.westerberg@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi: intel: Add support for second flash chipMika Westerberg2022-08-221-16/+147
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Intel SPI flash controller has been supporting two chip selects long time already even if the most common configuration is to have a single flash chip for the BIOS and related data. This adds support for the second chip select if we find out that there are two flash components (this information is available in the mandatory flash descriptor on the first chip). The second chip is exposed as is without any partition information. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20220816130818.89600-1-mika.westerberg@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi: move from strlcpy with unused retval to strscpyWolfram Sang2022-08-191-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Follow the advice of the below link and prefer 'strscpy' in this subsystem. Conversion is 1:1 because the return value is not used. Generated by a coccinelle script. Link: https://lore.kernel.org/r/CAHk-=wgfRnXz0W3D37d01q3JFkr_i_uTL=V6A6G1oUZcprmknw@mail.gmail.com/ Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20220818210107.7373-1-wsa+renesas@sang-engineering.com Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi: amd: Setup all xfers before opcode executionCristian Ciocaltea2022-08-181-46/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AMD SPI controller hardware seems to expect the FIFO buffer to be fully setup with the details of all transfers in the SPI message before it is able to start processing the data in a reliable way. Furthermore, it imposes a strict ordering restriction, in the sense that all TX transfers must be handled prior any RX transfer. Hence, let's ensure amd_spi_execute_opcode() is called only once, after all TX transfers have been setup, and process any remaining RX transfers afterwards, in a second iteration. Additionally, get rid of the unnecessary AMD_SPI_XFER_TX/RX defines and improve error handling. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20220818010059.403776-1-cristian.ciocaltea@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
| * | spi: npcm-pspi: add Arbel NPCM8XX supportMark Brown2022-08-151-0/+1
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | Merge series from Tomer Maimon <tmaimon77@gmail.com>: This patch set adds Arbel NPCM8XX Peripheral SPI (PSPI) support to PSPI NPCM driver.
| | * | spi: npcm-pspi: Add NPCM845 peripheral SPI supportTomer Maimon2022-08-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Nuvoton BMC NPCM845 NPCM Peripheral SPI (PSPI) support. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Link: https://lore.kernel.org/r/20220722114136.251415-3-tmaimon77@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
| * | | Add support for Microchip QSPI controllerMark Brown2022-08-153-0/+610
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge series from Naga Sureshkumar Relli <nagasuresh.relli@microchip.com>: This patch enables the Microchip's FPGA QSPI and Polarfire SoC QSPI controller support. Tested spi-nand (W25N01GV) and spi-nor (MT25QL256A) on Microchip's ICICLE kit. tested using both FPGA QSPI and Polarfie SoC QSPI.
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-15 08:56:06 +0000