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* Merge tag 'omap-for-v3.15/crossbar-signed' of ↵Olof Johansson2014-03-084-10/+289
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers Merge OMAP crossbar support from Tony Lindgren: Add support for GIC crossbar that routes interrupts on newer omaps. Looks like people wanted these merged via the omap tree as it's the only user for the GIC crossbar. * tag 'omap-for-v3.15/crossbar-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: DRA: Enable Crossbar IP support for DRA7XX ARM: OMAP4+: Correct Wakeup-gen code to use physical irq number DRIVERS: IRQCHIP: CROSSBAR: Add support for Crossbar IP DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs Signed-off-by: Olof Johansson <olof@lixom.net>
| * DRIVERS: IRQCHIP: CROSSBAR: Add support for Crossbar IPSricharan R2014-02-053-0/+217
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some socs have a large number of interrupts requests to service the needs of its many peripherals and subsystems. All of the interrupt lines from the subsystems are not needed at the same time, so they have to be muxed to the irq-controller appropriately. In such places a interrupt controllers are preceded by an CROSSBAR that provides flexibility in muxing the device requests to the controller inputs. This driver takes care a allocating a free irq and then configuring the crossbar IP as a part of the mpu's irqchip callbacks. crossbar_init should be called right before the irqchip_init, so that it is setup to handle the irqchip callbacks. Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Tony Lindgren <tony@atomide.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Grant Likely <grant.likely@linaro.org> Cc: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Sricharan R <r.sricharan@ti.com> Acked-by: Kumar Gala <galak@codeaurora.org> (for DT binding portion) Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Thomas Gleixner <tglx@linutronix.de>
| * DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqsSricharan R2014-02-051-10/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some socs the gic can be preceded by a crossbar IP which routes the peripheral interrupts to the gic inputs. The peripheral interrupts are associated with a fixed crossbar input line and the crossbar routes that to one of the free gic input line. The DT entries for peripherals provides the fixed crossbar input line as its interrupt number and the mapping code should associate this with a free gic input line. This patch adds the support inside the gic irqchip to handle such routable irqs. The routable irqs are registered in a linear domain. The registered routable domain's callback should be implemented to get a free irq and to configure the IP to route it. Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Tony Lindgren <tony@atomide.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Grant Likely <grant.likely@linaro.org> Cc: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Sricharan R <r.sricharan@ti.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
* | Merge tag 'mvebu-watchdog-3.15-2' of git://git.infradead.org/linux-mvebu ↵Olof Johansson2014-03-081-1/+1
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into next/drivers mvebu watchdog driver changes for v3.15 (incremental #2) - remove warnings by using %pa for phys_addr_t * tag 'mvebu-watchdog-3.15-2' of git://git.infradead.org/linux-mvebu: watchdog: orion_wdt: Use %pa to print 'phys_addr_t' Signed-off-by: Olof Johansson <olof@lixom.net>
| * | watchdog: orion_wdt: Use %pa to print 'phys_addr_t'Fabio Estevam2014-02-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When building an ARM multi_v7_defconfig with LPAE option selected we get the following build warning: drivers/watchdog/orion_wdt.c:272:2: warning: format '%x' expects argument of type 'unsigned int', but argument 4 has type 'phys_addr_t' [-Wformat=] Fix it by using %pa to print 'phys_addr_t'. Reported-by: Olof's autobuilder <build@lixom.net> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Wim Van Sebroeck <wim@iguana.be> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* | | Merge tag 'armsoc/for-3.15/drivers' of git://github.com/broadcom/mach-bcm ↵Arnd Bergmann2014-03-068-0/+2642
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into next/drivers Merge "ARM: mach-bcm: bcm281xx clock driver" from Matt Porter: This pull request contains the Broadcom bcm281xx clock driver series. This series is being merged through the arm-soc tree because there is an ordering dependency where the driver *must* be merged before the related dts changes. This is a result of the bcm281xx dts already containing dummy fixed clock nodes that must be updated. * tag 'armsoc/for-3.15/drivers' of git://github.com/broadcom/mach-bcm: clk: bcm281xx: don't disable unused peripheral clocks clk: bcm281xx: add initial clock framework support Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | | clk: bcm281xx: don't disable unused peripheral clocksAlex Elder2014-02-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the CLK_IGNORE_UNUSED flag when setting up a peripheral clock. This prevents unused clocks from getting disabled, and by doing this we can use the common clock code even before we've resolved all the spots that need to get a reference to their clock. Signed-off-by: Alex Elder <elder@linaro.org> Reviewed-by: Matt Porter <mporter@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Matt Porter <mporter@linaro.org>
| * | | clk: bcm281xx: add initial clock framework supportAlex Elder2014-02-248-0/+2642
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add code for device tree support of clocks in the BCM281xx family of SoCs. Machines in this family use peripheral clocks implemented by "Kona" clock control units (CCUs). (Other Broadcom SoC families use Kona style CCUs as well, but support for them is not yet upstream.) A BCM281xx SoC has multiple CCUs, each of which manages a set of clocks on the SoC. A Kona peripheral clock is composite clock that may include a gate, a parent clock multiplexor, and zero, one or two dividers. There is a variety of gate types, and many gates implement hardware-managed gating (often called "auto-gating"). Most dividers divide their input clock signal by an integer value (one or more). There are also "fractional" dividers which allow division by non-integer values. To accomodate such dividers, clock rates and dividers are generally maintained by the code in "scaled" form, which allows integer and fractional dividers to be handled in a uniform way. If present, the gate for a Kona peripheral clock must be enabled when a change is made to its multiplexor or one of its dividers. Additionally, dividers and multiplexors have trigger registers which must be used whenever the divider value or selected parent clock is changed. The same trigger is often used for a divider and multiplexor, and a BCM281xx peripheral clock occasionally has two triggers. The gate, dividers, and parent clock selector are treated in this code as "components" of a peripheral clock. Their functionality is implemented directly--e.g. the common clock framework gate implementation is not used for a Kona peripheral clock gate. (This has being considered though, and the intention is to evolve this code to leverage common code as much as possible.) The source code is divided into three general portions: drivers/clk/bcm/clk-kona.h drivers/clk/bcm/clk-kona.c These implement the basic Kona clock functionality, including the clk_ops methods and various routines to manipulate registers and interpret their values. This includes some functions used to set clocks to a desired initial state (though this feature is only partially implemented here). drivers/clk/bcm/clk-kona-setup.c This contains generic run-time initialization code for data structures representing Kona CCUs and clocks. This encapsulates the clock structure initialization that can't be done statically. Note that there is a great deal of validity-checking code here, making explicit certain assumptions in the code. This is mostly useful for adding new clock definitions and could possibly be disabled for production use. drivers/clk/bcm/clk-bcm281xx.c This file defines the specific CCUs used by BCM281XX family SoCs, as well as the specific clocks implemented by each. It declares a device tree clock match entry for each CCU defined. include/dt-bindings/clock/bcm281xx.h This file defines the selector (index) values used to identify a particular clock provided by a CCU. It consists entirely of C preprocessor constants, to be used by both the C source and device tree source files. Signed-off-by: Alex Elder <elder@linaro.org> Reviewed-by: Tim Kryger <tim.kryger@linaro.org> Reviewed-by: Matt Porter <mporter@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Matt Porter <mporter@linaro.org>
* | | | drivers: cci: Export CCI PMU revisionPunit Agrawal2014-02-251-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The event numbering changed between revision r0 and r1 of the CCI PMU. Expose this to userspace to allow tooling to handle the differences in event numbers. Suggested-by: Drew Richardson <Drew.Richardson@arm.com> Signed-off-by: Punit Agrawal <punit.agrawal@arm.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* | | | drivers: cci: Extend support to CCI revisions > r1p2Punit Agrawal2014-02-251-9/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver queries the CCI IP revision to distinguish between r0 and r1 scheme for event numbers and currently supports upto version r1p2. To minimise code churn every time there's a new version of the IP, assume that event numbering doesn't change for revisions > r1p0 (which is the case). The driver will still need an update for future revisions that change the event numbers. Signed-off-by: Punit Agrawal <punit.agrawal@arm.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* | | | Merge tag 'qcom-drivers-for-3.15' of ↵Arnd Bergmann2014-02-255-7/+7
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into next/drivers Merge "qcom driver changes for v3.15" from Kumar Gala: We've split Qualcomm MSM support into legacy and multiplatform. These drivers are only relevant on the multiplatform supported SoCs so switch the Kconfig depends to ARCH_QCOM. * tag 'qcom-drivers-for-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom: gpio: msm: switch Kconfig to ARCH_QCOM depends hwrng: msm: switch Kconfig to ARCH_QCOM depends power: reset: msm - switch Kconfig to ARCH_QCOM depends drm/msm: drop ARCH_MSM Kconfig depend tty: serial: msm: Enable building msm_serial for ARCH_QCOM
| * | | | gpio: msm: switch Kconfig to ARCH_QCOM dependsKumar Gala2014-02-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We've split Qualcomm MSM support into legacy and multiplatform. The gpio msm-v2 driver is only relevant on the multiplatform supported SoCs so switch the Kconfig depends to ARCH_QCOM. CC: Linus Walleij <linus.walleij@linaro.org> Acked-by: Alexandre Courbot <gnurou@gmail.com> Signed-off-by: Kumar Gala <galak@codeaurora.org>
| * | | | hwrng: msm: switch Kconfig to ARCH_QCOM dependsKumar Gala2014-02-211-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We've split Qualcomm MSM support into legacy and multiplatform. The RNG driver is only relevant on the multiplatform supported SoCs so switch the Kconfig depends to ARCH_QCOM. Acked-by: Herbert Xu <herbert@gondor.apana.org.au> CC: Stanimir Varbanov <svarbanov@mm-sol.com> Signed-off-by: Kumar Gala <galak@codeaurora.org>
| * | | | power: reset: msm - switch Kconfig to ARCH_QCOM dependsKumar Gala2014-02-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We've split Qualcomm MSM support into legacy and multiplatform. The reset driver is only relevant on the multiplatform supported SoCs so switch the Kconfig depends to ARCH_QCOM. Acked-by: Dmitry Eremin-Solenikov Signed-off-by: Kumar Gala <galak@codeaurora.org>
| * | | | drm/msm: drop ARCH_MSM Kconfig dependKumar Gala2014-02-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARCH_MSM depend is redundant with ARCH_MSM8960, so we can remove it. Additionally, we are splitting Qualcomm MSM support into legacy (ARCH_MSM) and multiplatform (ARCH_QCOM). The MSM8960 with be ARCH_QCOM going forward so dropping ARCH_MSM will work properly for the new ARCH_QCOM multiplatform build. Acked-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Kumar Gala <galak@codeaurora.org>
| * | | | tty: serial: msm: Enable building msm_serial for ARCH_QCOMKumar Gala2014-02-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We've split Qualcomm MSM support into legacy and multiplatform. So add the ability to build the serial driver on the newer ARCH_QCOM multiplatform. Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
* | | | | Merge branch 'qcom/cleanup' into next/driversArnd Bergmann2014-02-253-0/+334
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * qcom/cleanup: ARM: qcom: Rename various msm prefixed functions to qcom clocksource: qcom: split building of legacy vs multiplatform support ARM: qcom: Split Qualcomm support into legacy and multiplatform clocksource: qcom: Move clocksource code out of mach-msm ARM: msm: kill off hotplug.c ARM: msm: Remove pen_release usage ARM: dts: msm: split out msm8660 and msm8960 soc into dts include This cleanup branch is a dependency for the following qcom driver changes. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | | | clocksource: qcom: split building of legacy vs multiplatform supportKumar Gala2014-02-061-11/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The majority of the clocksource code for the Qualcomm platform is shared between newer (multiplatform) and older platforms. However there is a bit of code that isn't, so only build it for the appropriate config. Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Kumar Gala <galak@codeaurora.org>
| * | | | clocksource: qcom: Move clocksource code out of mach-msmKumar Gala2014-02-043-0/+333
| | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | We intend to share the clocksource code for MSM platforms between legacy and multiplatform supported qcom SoCs. Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Kumar Gala <galak@codeaurora.org>
* | | | irqchip: VIC: export vic_init_cascadedArnd Bergmann2014-02-251-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | vic_init_cascaded is called by integrator impd1 code that can be a loadable module, so the function has to be exported. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Linus Walleij <linus.walleij@linaro.org>
* | | | Merge tag 'mvebu-watchdog-3.15' of git://git.infradead.org/linux-mvebu into ↵Arnd Bergmann2014-02-252-80/+303
|\ \ \ \ | | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | next/drivers mvebu watchdog driver changes for v3.15 - orion watchdog - cleanup and extend driver to support Armada 370 and Armada XP Depends: - tags/irqchip-mvebu-fixes-3.14 (already pulled by tglx) - both are based on v3.14-rc1 * tag 'mvebu-watchdog-3.15' of git://git.infradead.org/linux-mvebu: watchdog: orion: Enable the build on ARCH_MVEBU watchdog: orion: Add support for Armada 370 and Armada XP SoC watchdog: orion: Add per-compatible watchdog start implementation watchdog: orion: Add per-compatible clock initialization watchdog: orion: Introduce per-compatible of_device_id data watchdog: orion: Introduce an orion_watchdog device structure watchdog: orion: Remove unneeded BRIDGE_CAUSE clear watchdog: orion: Make RSTOUT register a separate resource watchdog: orion: Handle the interrupt so it's properly acked watchdog: orion: Make sure the watchdog is initially stopped watchdog: orion: Remove unused macros watchdog: orion: Use atomic access for shared registers watchdog: orion: Add clock error handling Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | | watchdog: orion: Enable the build on ARCH_MVEBUEzequiel Garcia2014-02-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After adding support for Armada 370/XP SoC let's enable the build on these platforms. Reviewed-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Willy Tarreau <w@1wt.eu> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Wim Van Sebroeck <wim@iguana.be> Tested-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * | | watchdog: orion: Add support for Armada 370 and Armada XP SoCEzequiel Garcia2014-02-221-2/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using the added infrastructure for handling SoC differences, this commit adds support for the watchdog controller available in Armada 370 and Armada XP SoCs. Also, and because the AXP clock initialization uses of_clk_get_by_name, this commit changes the orion clock initialization to use clk_get() and adds a proper clk_put() on the common exit/error paths. Reviewed-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Willy Tarreau <w@1wt.eu> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Wim Van Sebroeck <wim@iguana.be> Tested-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * | | watchdog: orion: Add per-compatible watchdog start implementationEzequiel Garcia2014-02-221-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To handle differences between SoCs this commit adds per-compatible string start() function for the watchdog kick-off. This is preparation work and makes no functionality changes to the current driver. Reviewed-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Willy Tarreau <w@1wt.eu> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Wim Van Sebroeck <wim@iguana.be> Tested-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * | | watchdog: orion: Add per-compatible clock initializationEzequiel Garcia2014-02-221-21/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Following the introduction of the compatible-data field, it's now possible to further abstract the clock initialization. This will allow to support SoC with a different clock setup. Reviewed-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Willy Tarreau <w@1wt.eu> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Wim Van Sebroeck <wim@iguana.be> Tested-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * | | watchdog: orion: Introduce per-compatible of_device_id dataEzequiel Garcia2014-02-221-19/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds an orion_watchdog_data structure to hold compatible-data information. This allows to remove the driver-wide definition and to be able to add support for multiple compatible-strings in the future. Reviewed-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Willy Tarreau <w@1wt.eu> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Wim Van Sebroeck <wim@iguana.be> Tested-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * | | watchdog: orion: Introduce an orion_watchdog device structureEzequiel Garcia2014-02-221-45/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to prepare to support multiple compatible-strings, this commit adds a device structure to hold the driver's state. Reviewed-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Willy Tarreau <w@1wt.eu> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Wim Van Sebroeck <wim@iguana.be> Tested-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * | | watchdog: orion: Remove unneeded BRIDGE_CAUSE clearEzequiel Garcia2014-02-221-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After adding the IRQ request, the BRIDGE_CAUSE bit should be cleared by the bridge interrupt controller. There's no longer a need to do it in the watchdog driver, so we can simply remove it. Reviewed-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Willy Tarreau <w@1wt.eu> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Wim Van Sebroeck <wim@iguana.be> Tested-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * | | watchdog: orion: Make RSTOUT register a separate resourceEzequiel Garcia2014-02-221-3/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to support other SoC, it's required to distinguish the 'control' timer register, from the 'rstout' register that enables system reset on watchdog expiration. To prevent a compatibility break, this commit adds a fallback to a hardcoded RSTOUT address. Reviewed-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Willy Tarreau <w@1wt.eu> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Wim Van Sebroeck <wim@iguana.be> Tested-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * | | watchdog: orion: Handle the interrupt so it's properly ackedEzequiel Garcia2014-02-221-1/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DT-enabled plaforms, where the irqchip driver for the brigde interrupt controller is available, can handle the watchdog IRQ properly. Therefore, request the interrupt and add a dummy handler that merely calls panic(). This is done in order to have an initial 'ack' of the interruption, which clears the watchdog state. Furthermore, since some platforms don't have such IRQ, this commit makes the interrupt specification optional. Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Willy Tarreau <w@1wt.eu> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Wim Van Sebroeck <wim@iguana.be> Tested-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * | | watchdog: orion: Make sure the watchdog is initially stoppedEzequiel Garcia2014-02-221-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Having the watchdog initially fully stopped is important to avoid any spurious watchdog triggers, in case the registers are not in its reset state. If the watchdog rstout is enabled and the watchdog counter running, this initial stop is not performed, to comply with the 'nowayout' parameter. Reviewed-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Willy Tarreau <w@1wt.eu> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Wim Van Sebroeck <wim@iguana.be> Tested-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * | | watchdog: orion: Remove unused macrosEzequiel Garcia2014-02-221-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These are not used anywhere so it's safe to remove them. Reviewed-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Willy Tarreau <w@1wt.eu> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Wim Van Sebroeck <wim@iguana.be> Tested-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * | | watchdog: orion: Use atomic access for shared registersEzequiel Garcia2014-02-221-37/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the timer control register is shared with the clocksource driver, use the recently introduced atomic_io_clear_set() to access such register. Given the watchdog core already provides serialization for all the watchdog ops, this commit allows to remove the spinlock entirely. Reviewed-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Willy Tarreau <w@1wt.eu> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Wim Van Sebroeck <wim@iguana.be> Tested-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * | | watchdog: orion: Add clock error handlingEzequiel Garcia2014-02-221-10/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds a check for clk_prepare_enable success and introduces an error path to disable the clock properly. Reviewed-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Willy Tarreau <w@1wt.eu> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Wim Van Sebroeck <wim@iguana.be> Tested-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* | | | Merge tag 'irqchip-mvebu-fixes-3.14' of git://git.infradead.org/linux-mvebu ↵Arnd Bergmann2014-02-251-3/+19
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into next/drivers irqchip mvebu fixes for v3.14 - orion: - fixes for clearing bridge cause register, and clearing stale interrupts * tag 'irqchip-mvebu-fixes-3.14' of git://git.infradead.org/linux-mvebu: irqchip: orion: Fix getting generic chip pointer. irqchip: orion: clear stale interrupts in irq_startup irqchip: orion: use handle_edge_irq on bridge irqs irqchip: orion: clear bridge cause register on init This is a dependency for the mvebu watchdog changes. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | | irqchip: orion: Fix getting generic chip pointer.Andrew Lunn2014-02-211-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enabling SPARSE_IRQ shows up a bug in the irq-orion bridge interrupt handler. The bridge interrupt is implemented using a single generic chip. Thus the parameter passed to irq_get_domain_generic_chip() should always be zero. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Fixes: 9dbd90f17e4f ("irqchip: Add support for Marvell Orion SoCs") Cc: <stable@vger.kernel.org> # v3.11+ Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * | | irqchip: orion: clear stale interrupts in irq_startupSebastian Hesselbarth2014-02-061-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bridge IRQ_CAUSE bits are asserted regardless of the corresponding bit in IRQ_MASK register. To avoid interrupt events on stale irqs, we have to clear them before unmask. This installs an .irq_startup callback to ensure stale irqs are cleared before initial unmask. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Cc: <stable@vger.kernel.org>: f56c0738b5c2: "irqchip: orion: clear bridge cause register on init" Cc: <stable@vger.kernel.org>: 38bd80b84fca: "irqchip: orion: use handle_edge_irq on bridge irqs" Cc: <stable@vger.kernel.org> # v3.10+ Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * | | irqchip: orion: use handle_edge_irq on bridge irqsSebastian Hesselbarth2014-02-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bridge irqs are edge-triggered, i.e. they get asserted on low-to-high transitions and not on the level of the downstream interrupt line. This replaces handle_level_irq by the more appropriate handle_edge_irq. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Cc: <stable@vger.kernel.org>: f56c0738b5c2: "irqchip: orion: clear bridge cause register on init" Cc: <stable@vger.kernel.org> # v3.10+ Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * | | irqchip: orion: clear bridge cause register on initSebastian Hesselbarth2014-02-061-1/+2
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | It is good practice to mask and clear pending irqs on init. We already mask all irqs, so also clear the bridge irq cause register. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Cc: <stable@vger.kernel.org> # v3.10+ Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* | | Merge tag 'davinci-for-v3.15/nand' of ↵Arnd Bergmann2014-02-251-22/+0
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/drivers A patch to break dependency of DaVinci NAND driver with mach-davinci. Required for reuse of driver on other platforms (keystone). * tag 'davinci-for-v3.15/nand' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci: ARM: davinci: aemif: get rid of davinci-nand driver dependency on aemif Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | | ARM: davinci: aemif: get rid of davinci-nand driver dependency on aemifIvan Khoronzhuk2014-02-231-22/+0
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The problem that the set timings code contains the call of Davinci platform function davinci_aemif_setup_timing() which is not accessible if kernel is built for another platform like Keystone. The Keysone platform is going to use TI AEMIF driver. If TI AEMIF is used we don't need to set timings and bus width. It is done by AEMIF driver. To get rid of davinci-nand driver dependency on aemif platform code we moved aemif code to davinci platform. The platform AEMIF code (aemif.c) has to be removed once Davinci will be converted to DT and use ti-aemif.c driver. Acked-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> [nsekhar@ti.com: fixed checkpatch error and a build breakage due to missing include, rebased onto l2-mtd/master] Signed-off-by: Sekhar Nori <nsekhar@ti.com>
* | | Merge tag 'integrator-for-v3.15-1' of ↵Olof Johansson2014-02-216-64/+110
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into next/drivers Merge "Integrator/Versatile base patch stack for the v3.15 series" from Linus Walleij: "this is a set of patches I have sent for review and failed to get ACKs from the proper subsystem maintainers after repeated pings. However I now need to have this rotated in linux-next as a base for multiplatform, so please pull it in, it is all ARM drivers anyway. Russell pointed out some things and these have been fixed and iterated in this series." - Move integrator clock definitions to the device tree, alter clock and timer drivers accordingly. - Alter the VIC irqchip driver to support cascaded VICs off a parent IRQ controller. - Update the IM-PD1 plugin code to use managed resources. - Register the VIC on the IM-PD1. - Select the PL061 GPIO block for the IM-PD1 on the Integrator/AP. * tag 'integrator-for-v3.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator: ARM: integrator: select GPIO block ARM: integrator: register the IM-PD1 VIC ARM: integrator: use managed resources for the IM-PD1 irqchip: support cascaded VICs irqchip: vic: update the base IRQ member correctly clk: versatile: respect parent rate in ICST clock clk: versatile: pass a parent to the ICST clock ARM: integrator: switch to fetch clocks from device tree ARM: SP804: make Integrator/CP timer pick clock from DT ARM: integrator: define clocks in the device trees Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | irqchip: support cascaded VICsLinus Walleij2014-02-131-6/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for a VIC to be cascaded off another IRQ. On the Integrator/AP logical module IM-PD1 there is a VIC cascaded off the central FPGA IRQ controller so this is needed for that to work out. In order for the plug-in board to be able to register all the devices with their IRQs relative to the offset of the base obtained for the cascaded VIC, the base IRQ number is passed back to the caller. Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | irqchip: vic: update the base IRQ member correctlyLinus Walleij2014-02-131-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When passing 0 as the irq base the VIC driver will dynamically allocate a number of consecutive interrupt descriptors at some available number range. Make sure this number is recorded in the state container rather than the passed-in zero argument in this case. Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | clk: versatile: respect parent rate in ICST clockLinus Walleij2014-02-132-5/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the ICST clock has a parent, respect the rate of the parent when calculating the clock frequency. As this involves modifying the ICST parameter struct, make a cloned copy (the divisor arrays should be safe) so we can update the .ref field. Do not define the reference clock on the Integrator as we have the reference clock from the device tree. Keep it everywhere else. Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | clk: versatile: pass a parent to the ICST clockLinus Walleij2014-02-135-5/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As we want to actually define the parent frequency in the device tree for the ICST clocks, modify the clock registration function to take a parent argument. Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | ARM: integrator: switch to fetch clocks from device treeLinus Walleij2014-02-131-48/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This atomic commit changes the Integrator clock implementation and the machines to register clocks from the device tree and use these instead of the previous hard-coded clocks. In the clock implementation all hard-coded clocks and the special initialization function call goes away, and is replaced by two compatible strings for the two clocks available on the core module. Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | | Merge tag 'renesas-soc-for-v3.15' of ↵Olof Johansson2014-02-201-0/+38
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers Merge "Renesas ARM Based SoC Updates for v3.15" from Simon Horman: * r7s72100 SoC (RZ/A1H) - Add i2c clocks (portion missing from previous patch due to miss-merge) * r8a7791 (R-Car M2) - Add SATA clocks - Add ZS clock - Wait for status on all MSTP clocks -- Add I2C and VIN clocks * r8a7790 (R-Car H2) - Add PCI USB host clock support - Add Audio DMAC, SATA and VIN clocks - Add Audio DMAC support * r8a7779 (R-Car H1) - Wait for status on selected MSTP clocks * tag 'renesas-soc-for-v3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: r8a7790: Add PCI USB host clock support ARM: shmobile: r7s72100: really add i2c clocks ARM: shmobile: r8a7791: Add SATA clocks ARM: shmobile: r8a7791: Add ZS clock ARM: shmobile: r8a7790: Add SATA clocks ARM: shmobile: r8a7790: Add VIN clock support ARM: shmobile: r8a7790: add Audio DMAC support ARM: shmobile: r8a7790: add Audio DMAC clock ARM: shmobile: r8a7791: Wait for status on all MSTP clocks ARM: shmobile: r8a7791: Add VIN clocks ARM: shmobile: r8a7791: Add I2C clocks ARM: shmobile: r8a7790: Wait for status on all MSTP clocks ARM: shmobile: r8a7779: Wait for status on selected MSTP clocks ARM: shmobile: wait for MSTP clock status to toggle, when enabling it
| * | | | ARM: shmobile: wait for MSTP clock status to toggle, when enabling itGuennadi Liakhovetski2014-02-041-0/+38
| | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On r-/sh-mobile SoCs MSTP clocks are used by the runtime PM to dynamically enable and disable peripheral clocks. To make sure the clock has really started we have to read back its status register until it confirms success. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | | | Merge tag 'dma-buf-for-3.14' of ↵Linus Torvalds2014-02-171-13/+12
|\ \ \ \ | |_|_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/sumits/dma-buf Pull dma-buf fix from Sumit Semwal: "Just some debugfs output updates. There's another patch related to dma-buf, but it'll get upstreamed via Greg KH's pull request" * tag 'dma-buf-for-3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/sumits/dma-buf: dma-buf: update debugfs output
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-21 12:44:25 +0000