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| | * | mtd: spi-nor: shorten Kconfig namingBrian Norris2014-04-144-6/+11
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Huang Shijie <b32955@freescale.com>
| | * | mtd: spi-nor: unify read opcode variants with ST SPI FSMBrian Norris2014-04-142-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | serial_flash_cmds.h defines our opcodes a little differently. Let's borrow its naming, since it's borrowed from the SFDP standard, and it's more extensible. This prepares us for merging serial_flash_cmds.h and spi-nor.h opcode listing. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Huang Shijie <b32955@freescale.com>
| | * | mtd: spi-nor: re-name OPCODE_* to SPINOR_OP_*Brian Norris2014-04-143-63/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Qualify these with a better namespace, and prepare them for use in more drivers. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Huang Shijie <b32955@freescale.com>
| | * | mtd: spi-nor: add the copyright informationHuang Shijie2014-04-141-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the copyright information for spi-nor.c and spi-nor.h. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| | * | mtd: st_spi_fsm: Add support for Macronix MX25L3255EAngus Clark2014-04-141-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the Macronix MX25L3255E device. Unlike the other Macronix devices we have seen, this device supports WRITE_1_4_4 at reasonable frequencies. Rather than masking out WRITE_1_4_4 support altogether, we now rely on the table parameters to indicate whether or not WRITE_1_4_4 should be used. Signed-off-by: Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| | * | mtd: st_spi_fsm: Add Spansion S25FL032P to device tableAngus Clark2014-04-141-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Spansion S25FL032P to the list of known devices. Signed-off-by: Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| | * | mtd: st_spi_fsm: Refactor status register operationsAngus Clark2014-04-141-84/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch refactors the fsm_read_status() and fsm_write_status() code to support 1 or 2 byte operations, with a specified command. This allows us to remove device/register specific code, such as the N25Q fsm_wrvcr() function. The 'QE' configuration code is updated accordingly, with minor tweaks to ensure the register values are only written if actually required. One notable change in this area is that the 'W25Q_STATUS_QE' bit-field is now defined with respect to the 'SR2' register, rather than the combined 'SR1+SR2' register which is only used for write operations. Signed-off-by: Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| | * | mtd: st_spi_fsm: Update Macronix 'QE' configurationAngus Clark2014-04-141-4/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the configuration of the Macronix 'QE' bit, such that we only set or clear the bit if required. Signed-off-by: Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| | * | mtd: st_spi_fsm: Update Macronix 32-bit addressing supportAngus Clark2014-04-141-13/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support for the Macronix 32-bit addressing scheme was originally developed using the MX25L25635E device. As is often the case, it was found that the presence of a "WAIT" instruction was required for the "EN4B/EX4B" FSM Sequence to complete. (It is known that the SPI FSM Controller makes certain undocumented assumptions regarding what constitutes a valid sequence.) However, further testing suggested that a small delay was required after issuing the "EX4B" command; without this delay, data corruptions were observed, consistent with the device not being ready to retrieve data. Although the issue was not fully understood, the workaround of adding a small delay was implemented, while awaiting clarification from Macronix. The same behaviour has now been found with a second Macronix device, the MX25L25655E. However, with this device, it seems that the delay is also required after the 'EN4B' commands. This discovery has prompted us to revisit the issue. Although still not conclusive, further tests have suggested that the issue is down to the SPI FSM Controller, rather than the Macronix devices. Furthermore, an alternative workaround has emerged which is to set the WAIT time to 0x00000001, rather then 0x00000000. (Note, the WAIT instruction is used purely for the purpose of achieving "sequence validity", rather than actually implementing a delay!) The issue is now being investigated by the Design and Validation teams. In the meantime, we implement the alternative workaround, which reduces the effective delay from 1us to 1ns. Signed-off-by: Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| | * | mtd: st_spi_fsm: Add Macronix MX25L25655E deviceAngus Clark2014-04-141-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Macronix MX25L25655E to the list of known devices. Signed-off-by: Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| | * | mtd: spi-nor: EXPORT symbols which could be used by module driversBrian Norris2014-04-141-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix errors like this: ERROR: "spi_nor_ids" [drivers/mtd/devices/m25p80.ko] undefined! ERROR: "spi_nor_scan" [drivers/mtd/devices/m25p80.ko] undefined! make[1]: *** [__modpost] Error 1 make: *** [modules] Error 2 Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| | * | mtd: spi-nor: Add Freescale QuadSPI driverHuang Shijie2014-04-143-0/+1016
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (0) What is the QuadSPI controller? The QuadSPI(Quad Serial Peripheral Interface) acts as an interface to one single or two external serial flash devices, each with up to 4 bidirectional data lines. (1) The QuadSPI controller is driven by the LUT(Look-up Table) registers. The LUT registers are a look-up-table for sequences of instructions. A valid sequence consists of four LUT registers. (2) The definition of the LUT register shows below: --------------------------------------------------- | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 | --------------------------------------------------- There are several types of INSTRx, such as: CMD : the SPI NOR command. ADDR : the address for the SPI NOR command. DUMMY : the dummy cycles needed by the SPI NOR command. .... There are several types of PADx, such as: PAD1 : use a singe I/O line. PAD2 : use two I/O lines. PAD4 : use quad I/O lines. .... (3) Test this driver with the JFFS2 and UBIFS: For jffs2: ------------- #flash_eraseall /dev/mtd0 #mount -t jffs2 /dev/mtdblock0 tmp #bonnie++ -d tmp -u 0 -s 10 -r 5 For ubifs: ------------- #flash_eraseall /dev/mtd0 #ubiattach /dev/ubi_ctrl -m 0 #ubimkvol /dev/ubi0 -N test -m #mount -t ubifs ubi0:test tmp #bonnie++ -d tmp -u 0 -s 10 -r 5 Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| | * | mtd: spi-nor: add a helper to find the spi_device_idHuang Shijie2014-04-141-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the spi_nor_match_id() to find the proper spi_device_id with the NOR flash's name in the spi_nor_ids table. Signed-off-by: Huang Shijie <b32955@freescale.com> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| | * | mtd: m25p80: use the SPI nor frameworkBrian Norris2014-04-142-1199/+106
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the new SPI nor framework, and rewrite the m25p80: (0) remove all the NOR comands. (1) change the m25p->command to an array. (2) implement the necessary hooks, such as m25p80_read/m25p80_write. Tested with the m25p32. Signed-off-by: Huang Shijie <b32955@freescale.com> Acked-by: Marek Vasut <marex@denx.de> [Brian: rebased] Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| | * | mtd: spi-nor: add the framework for SPI NORHuang Shijie2014-04-145-0/+1098
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch cloned most of the m25p80.c. In theory, it adds a new spi-nor layer. Before this patch, the layer is like: MTD ------------------------ m25p80 ------------------------ spi bus driver ------------------------ SPI NOR chip After this patch, the layer is like: MTD ------------------------ spi-nor ------------------------ m25p80 ------------------------ spi bus driver ------------------------ SPI NOR chip With the spi-nor controller driver(Freescale Quadspi), it looks like: MTD ------------------------ spi-nor ------------------------ fsl-quadspi ------------------------ SPI NOR chip New APIs: spi_nor_scan: used to scan a spi-nor flash. Signed-off-by: Huang Shijie <b32955@freescale.com> Acked-by: Marek Vasut <marex@denx.de> [Brian: rebased to include additional m25p_ids[] entry] Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * | | mtd: gpmi: add gpmi_devdata{} to simplify the codeHuang Shijie2014-04-163-40/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | More and more chips use the GPMI controller, but these chips may use different version of the IPs for GPMI and BCH. Different IPs have different features, such as the BCH's maximum ECC strength: imx23/imx28 -- the BCH's maximum ECC strength is 20 imx6q -- the BCH's maximum ECC strength is 40 imx6sx -- the BCH's maximum ECC strength is 62 This patch does the following things: [1] add a new data structure, gpmi_devdata{}, to store the information for each IP. Besides the IP version, we store the following information: <1> BCH's maximum ECC strength. <2> the maximum chain delay in ns used by the EDO mode. but we may add more information in future. [2] add the gpmi_devdata_imx{23|28|6q} to replace the gpmi_ids. [3] simplify the code by using the ECC strength from gpmi_devdata, such as gpmi_check_ecc() and legacy_set_geometry(); [4] use the maximum chain delay to initialize the EDO mode, see gpmi_compute_edo_timing(). [5] rewrite the macros, such GPMI_IS_MX{23|28|6Q}. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * | | mtd: nand: add line feed to pr_errRaphaël Poggi2014-04-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add line feed to pr_err. Signed-off-by: Raphaël Poggi <poggi.raph@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * | | mtd: davinci-nand: disable subpage write for keystone-nandMurali Karicheri2014-04-151-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sub page write doesn't work because of hw issue in controller found on Keystone SOCs. AEMIF controller is also used on DaVinci SOCs which don't seems to have any issue. So add "ti,keysone-nand" compatible to nand driver in order to set NAND_NO_SUBPAGE_WRITE option. Cc: Warner Losh <imp@bsdimp.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * | | mtd: mtd_blkdevs: handle REQ_FLUSH request and do explicit flush of ↵Roman Peniaev2014-04-151-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | writeback buffer mtd_blkdevs is device with volatile cache (writeback buffer), so it should support REQ_FLUSH to do explicit flush. Without this patch 'sync' does not guarantee that writeback buffer will be flushed on disk in case of power off, e.g.: $ cp some_file /mnt $ sync ### POWER OFF In case of this sequence writeback buffer will not be flushed on disk. This patch fixes this behaviour and explicitly reports to block layer that flush requests are being supported. Signed-off-by: Roman Peniaev <r.peniaev@gmail.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: linux-mtd@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * | | mtd: nand: use the nand_read_subpage index everywhereRon2014-04-151-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the index variable is correctly set earlier in this function we can use it in other places that compute the same thing too. Signed-off-by: Ron Lee <ron@debian.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * | | mtd: nand: omap: fix compile warning on ‘erased_sector_bitflips’Christian Engelmayer2014-04-151-1/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 2c9f2365 (mtd: nand: omap: ecc.calculate: merge omap3_calculate_ecc_bch4 in omap_calculate_ecc_bch) introduced minor compile warning "‘erased_sector_bitflips’ defined but not used [-Wunused-function]" when compiling without CONFIG_MTD_NAND_OMAP_BCH. Move function erased_sector_bitflips() into the same ifdef section as the only caller. Signed-off-by: Christian Engelmayer <cengelma@gmx.at> Reviewed-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* | | Merge tag 'md/3.16' of git://neil.brown.name/mdLinus Torvalds2014-06-114-42/+138
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull md updates from Neil Brown: "Assorted md fixes for 3.16 Mostly performance improvements with a few corner-case bug fixes" * tag 'md/3.16' of git://neil.brown.name/md: raid5: speedup sync_request processing md/raid5: deadlock between retry_aligned_read with barrier io raid5: add an option to avoid copy data from bio to stripe cache md/bitmap: remove confusing code from filemap_get_page. raid5: avoid release list until last reference of the stripe md: md_clear_badblocks should return an error code on failure. md/raid56: Don't perform reads to support writes until stripe is ready. md: refuse to change shape of array if it is active but read-only
| * | | raid5: speedup sync_request processingEivind Sarto2014-06-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The raid5 sync_request() processing calls handle_stripe() within the context of the resync-thread. The resync-thread issues the first set of read requests and this adds execution latency and slows down the scheduling of the next sync_request(). The current rebuild/resync speed of raid5 is not much faster than what rotational HDDs can sustain. Testing the following patch on a 6-drive array, I can increase the rebuild speed from 100 MB/s to 175 MB/s. The sync_request() now just sets STRIPE_HANDLE and releases the stripe. This creates some more parallelism between the resync-thread and raid5 kernel daemon. Signed-off-by: Eivind Sarto <esarto@fusionio.com> Signed-off-by: NeilBrown <neilb@suse.de>
| * | | md/raid5: deadlock between retry_aligned_read with barrier iohui jiao2014-06-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A chunk aligned read increases counter active_aligned_reads and decreases it after sub-device handle it successfully. But when a read error occurs, the read redispatched by raid5d, and the active_aligned_reads will not be decreased until we can grab a stripe head in retry_aligned_read. Now suppose, a barrier io comes, set conf->quiesce to 2, and wait until both active_stripes and active_aligned_reads are zero. The retried chunk aligned read gets stuck at get_active_stripe waiting until conf->quiesce becomes 0. Retry_aligned_read and barrier io are waiting each other now. One possible solution is that we ignore conf->quiesce, let the retried aligned read finish. I reproduced this deadlock and test this patch on centos6.0 Signed-off-by: NeilBrown <neilb@suse.de>
| * | | raid5: add an option to avoid copy data from bio to stripe cacheShaohua Li2014-05-292-22/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The stripe cache has two goals: 1. cache data, so next time if data can be found in stripe cache, disk access can be avoided. 2. stable data. data is copied from bio to stripe cache and calculated parity. data written to disk is from stripe cache, so if upper layer changes bio data, data written to disk isn't impacted. In my environment, I can guarantee 2 will not happen. And BDI_CAP_STABLE_WRITES can guarantee 2 too. For 1, it's not common too. block plug mechanism will dispatch a bunch of sequentail small requests together. And since I'm using SSD, I'm using small chunk size. It's rare case stripe cache is really useful. So I'd like to avoid the copy from bio to stripe cache and it's very helpful for performance. In my 1M randwrite tests, avoid the copy can increase the performance more than 30%. Of course, this shouldn't be enabled by default. It's reported enabling BDI_CAP_STABLE_WRITES can harm some workloads before, so I added an option to control it. Neilb: changed BUG_ON to WARN_ON Removed some assignments from raid5_build_block which are now not needed. Signed-off-by: Shaohua Li <shli@fusionio.com> Signed-off-by: NeilBrown <neilb@suse.de>
| * | | md/bitmap: remove confusing code from filemap_get_page.NeilBrown2014-05-291-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | file_page_index(store, 0) is *always* 0. This is because the bitmap sb, at 256 bytes, is *always* less than one page. So subtracting it has no effect and the code should be removed. Reported-by: Goldwyn Rodrigues <rgoldwyn@suse.de> Signed-off-by: NeilBrown <neilb@suse.de>
| * | | raid5: avoid release list until last reference of the stripeEivind Sarto2014-05-291-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The (lockless) release_list reduces lock contention, but there is excessive queueing and dequeuing of stripes on this list. A stripe will currently be queued on the release_list with a stripe reference count > 1. This can cause the raid5 kernel thread(s) to dequeue the stripe and decrement the refcount without doing any other useful processing of the stripe. The are two cases when the stripe can be put on the release_list multiple times before it is actually handled by the kernel thread(s). 1) make_request() activates the stripe processing in 4k increments. When a write request is large enough to span multiple chunks of a stripe_head, the first 4k chunk adds the stripe to the plug list. The next 4k chunk that is processed for the same stripe puts the stripe on the release_list with a refcount=2. This can cause the kernel thread to process and decrement the stripe before the stripe us unplugged, which again will put it back on the release_list. 2) Whenever IO is scheduled on a stripe (pre-read and/or write), the stripe refcount is set to the number of active IO (for each chunk). The stripe is released as each IO complete, and can be queued and dequeued multiple times on the release_list, until its refcount finally reached zero. This simple patch will ensure a stripe is only queued on the release_list when its refcount=1 and is ready to be handled by the kernel thread(s). I added some instrumentation to raid5 and counted the number of times striped were queued on the release_list for a variety of write IO sizes. Without this patch the number of times stripes got queued on the release_list was 100-500% higher than with the patch. The excess queuing will increase with the IO size. The patch also improved throughput by 5-10%. Signed-off-by: Eivind Sarto <esarto@fusionio.com> Signed-off-by: NeilBrown <neilb@suse.de>
| * | | md: md_clear_badblocks should return an error code on failure.NeilBrown2014-05-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Julia Lawall and coccinelle report that md_clear_badblocks always returns 0, despite appearing to have an error path. The error path really should return an error code. ENOSPC is reasonably appropriate. Reported-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: NeilBrown <neilb@suse.de>
| * | | md/raid56: Don't perform reads to support writes until stripe is ready.NeilBrown2014-05-291-12/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If it is found that we need to pre-read some blocks before a write can succeed, we normally set STRIPE_DELAYED and don't actually perform the read until STRIPE_PREREAD_ACTIVE subsequently gets set. However for a degraded RAID6 we currently perform the reads as soon as we see that a write is pending. This significantly hurts throughput. So: - when handle_stripe_dirtying find a block that it wants on a device that is failed, set STRIPE_DELAY, instead of doing nothing, and - when fetch_block detects that a read might be required to satisfy a write, only perform the read if STRIPE_PREREAD_ACTIVE is set, and if we would actually need to read something to complete the write. This also helps RAID5, though less often as RAID5 supports a read-modify-write cycle. For RAID5 the read is performed too early only if the write is not a full 4K aligned write (i.e. no an R5_OVERWRITE). Also clean up a couple of horrible bits of formatting. Reported-by: Patrik Horník <patrik@dsl.sk> Signed-off-by: NeilBrown <neilb@suse.de>
| * | | md: refuse to change shape of array if it is active but read-onlyNeilBrown2014-05-291-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | read-only arrays should not be changed. This includes changing the level, layout, size, or number of devices. So reject those changes for readonly arrays. Signed-off-by: NeilBrown <neilb@suse.de>
* | | | Merge git://www.linux-watchdog.org/linux-watchdogLinus Torvalds2014-06-1016-1134/+608
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull watchdog updates from Wim Van Sebroeck: "This contains: - addition of the Intel MID watchdog - removal of W83697HF and W83697UG drivers (code was merged into w83627hf_wdt driver) - addition of Armada 375/380 SoC support - conversion of imx2_wdt to regmap API and to watchdog core API - lots of other small improvements and fixes" [ Wim was also tagged by gmail as a spammer, but not delayed by days unlike Ben ] * git://www.linux-watchdog.org/linux-watchdog: (25 commits) x86: intel-mid: add watchdog platform code for Merrifield watchdog: add Intel MID watchdog driver support watchdog: sp805: Set watchdog_device->timeout from ->set_timeout() booke/watchdog: refine and clean up the codes watchdog: iop_wdt only builds for mach-iop13xx watchdog: Remove drivers for W83697HF and W83697UG watchdog: w83627hf_wdt: Add early_disable module parameter ARM: mvebu: Add A375/A380 watchdog binding documentation watchdog: orion: Add Armada 375/380 SoC support watchdog: orion: Introduce per-SoC enabled() function watchdog: orion: Introduce per-SoC stop() function watchdog: orion: Remove unneeded atomic access watchdog: orion: Introduce a SoC-specific RSTOUT mapping watchdog: orion: Move the register ioremap'ing to its own function watchdog: xilinx: Make of_device_id array const watchdog: imx2_wdt: convert to watchdog core api watchdog: imx2_wdt: convert to use regmap API. watchdog: imx2_wdt: Sort the header files alphabetically watchdog: ath79_wdt: switch to clk_prepare/clk_disable watchdog: ath79_wdt: avoid spurious restarts on AR934x ...
| * | | | watchdog: add Intel MID watchdog driver supportDavid Cohen2014-06-103-0/+198
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial Intel MID watchdog driver support. This driver is an initial implementation of generic Intel MID watchdog driver. Currently it supports Intel Merrifield platform. Signed-off-by: Eric Ernst <eric.ernst@intel.com> Signed-off-by: David Cohen <david.a.cohen@linux.intel.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
| * | | | watchdog: sp805: Set watchdog_device->timeout from ->set_timeout()Viresh Kumar2014-06-101-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implementation of ->set_timeout() is supposed to set 'timeout' field of 'struct watchdog_device' passed to it. sp805 was rather setting this in a local variable. Fix it. Reported-by: Arun Ramamurthy <arun.ramamurthy@broadcom.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be> Cc: <stable@vger.kernel.org> # 2.6.36+
| * | | | booke/watchdog: refine and clean up the codesTang Yuantian2014-06-101-18/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Basically, this patch does the following: 1. Move the codes of parsing boot parameters from setup-common.c to driver. In this way, code reader can know directly that there are boot parameters that can change the timeout. 2. Make boot parameter 'booke_wdt_period' effective. currently, when driver is loaded, default timeout is always being used in stead of booke_wdt_period. 3. Wrap up the watchdog timeout in device struct and clean up unnecessary codes. Signed-off-by: Tang Yuantian <yuantian.tang@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: Li Yang <leoli@freescale.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
| * | | | watchdog: iop_wdt only builds for mach-iop13xxArnd Bergmann2014-06-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All three iop variants we support in Linux (iop32x, iop33x and iop13xx) seem to have support for the watchdog hardware, but this driver fails to build for the first two of these because it uses the IOP13XX_WDTCR_IB_RESET macro that is only defined for iop13xx. This clarifies the dependency in Kconfig to avoid randconfig build errors. It is unlikely that anyone will ever miss support for this driver on the ancient iop3xx platforms, so we don't need to bother trying to fix it properly. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be> Cc: linux-watchdog@vger.kernel.org
| * | | | watchdog: Remove drivers for W83697HF and W83697UGGuenter Roeck2014-06-104-889/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since both chips are now supported by the w83627hf watchdog driver, the chip specific drivers are no longer needed and can be removed. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
| * | | | watchdog: w83627hf_wdt: Add early_disable module parameterGuenter Roeck2014-06-101-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add early_disable module parameter to match functionality previously available in the w83697hf_wdt driver. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
| * | | | watchdog: orion: Add Armada 375/380 SoC supportEzequiel Garcia2014-06-101-0/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds support for the Armada 375 and Armada 380 SoCs. This SoC variant has a second RSTOUT register, in addition to the already existent, which is shared with the system-controller. To handle this RSTOUT, we introduce a new MMIO register 'rstout_mask' to be required on 'armada-{375,380}-watchdog' new compatible string. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Jason Cooper <jason@lakedaemon.net> Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
| * | | | watchdog: orion: Introduce per-SoC enabled() functionEzequiel Garcia2014-06-101-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to support other SoCs, it's needed to have a different enabled() implementation for each SoC. This commit adds no functionality, and it consists of preparation work. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Jason Cooper <jason@lakedaemon.net> Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
| * | | | watchdog: orion: Introduce per-SoC stop() functionEzequiel Garcia2014-06-101-1/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to support other SoCs, it's needed to have a different stop() implementation for each SoC. This commit adds no functionality, and it consists of preparation work. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Jason Cooper <jason@lakedaemon.net> Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
| * | | | watchdog: orion: Remove unneeded atomic accessEzequiel Garcia2014-06-101-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RSTOUT register on the Armada 370 SoC variant is a dedicated register (not shared across orthogonal subsystems) and so it's not needed to write it atomically. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Jason Cooper <jason@lakedaemon.net> Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
| * | | | watchdog: orion: Introduce a SoC-specific RSTOUT mappingEzequiel Garcia2014-06-101-7/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Separate the RSTOUT register mapping for the different compatible strings supported by the driver. This allows to use devm_ioremap on SoC variants that share the RSTOUT register, and devm_ioremap_resource (which requests the MMIO region) on SoCs that have a dedicated RSTOUT register. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Jason Cooper <jason@lakedaemon.net> Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
| * | | | watchdog: orion: Move the register ioremap'ing to its own functionEzequiel Garcia2014-06-101-14/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Follow-up patches will extend the registers ioremap and request to handle SoC-specific quirks on the RSTOUT register. Therefore, in order to keep the code readable, this commit introduces a special function for this. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Jason Cooper <jason@lakedaemon.net> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
| * | | | watchdog: xilinx: Make of_device_id array constJingoo Han2014-06-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make of_device_id array const, because all OF functions handle it as const. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Reviewed-by: Michal Simek <monstr@monstr.eu> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
| * | | | watchdog: imx2_wdt: convert to watchdog core apiAnatolij Gustschin2014-06-102-170/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the imx2_wdt driver to the new watchdog core api. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Cc: Wolfram Sang <wsa@the-dreams.de> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
| * | | | watchdog: imx2_wdt: convert to use regmap API.Xiubo Li2014-06-102-18/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This watchdog driver will be working on IMX2+, Vybrid, LS1, LS2+ platforms, and will be in different endianness mode in those SoCs: SoCs CPU endian mode WDT endian mode ------------------------------------------------ IMX2+ LE LE Vybird LE LE LS1 LE BE LS2 LE LE Other possible SoCs: SoCs CPU endian mode WDT endian mode ------------------------------------------------ Soc1 BE BE Soc2 BE LE And also the watchdog's registers will be 32-bits for some versions, and though it is 16-bits in IMX2+, Vybird and LS+. Using the regmap APIs, could be more easy to support different endianness and also more easy to support 32-bits version... Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
| * | | | watchdog: imx2_wdt: Sort the header files alphabeticallyXiubo Li2014-06-101-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
| * | | | watchdog: ath79_wdt: switch to clk_prepare/clk_disableGabor Juhos2014-06-101-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace clk_enable() and clk_disable() calls with clk_prepare_enable() and clk_disable_unprepare() to get ready for the migration to the common clock framework. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
| * | | | watchdog: ath79_wdt: avoid spurious restarts on AR934xGabor Juhos2014-06-101-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some AR934x based systems, where the frequency of the AHB bus is relatively high, the built-in watchdog causes a spurious restart when it gets enabled. The possible cause of these restarts is that the timeout value written into the TIMER register does not reaches the hardware in time. Add an explicit delay into the ath79_wdt_enable function to avoid the spurious restarts. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be> Cc: <stable@vger.kernel.org>
| * | | | watchdog: shwdt: Remove unused platform_set_drvdata()Alexander Shiyan2014-06-101-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes platform_set_drvdata() which is not used in the driver. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-09 07:49:22 +0000