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* net: remove ndo_udp_tunnel_* callbacksJakub Kicinski2021-01-0720-48/+0
| | | | | | | | | All UDP tunnel port management is now routed via udp_tunnel_nic infra directly. Remove the old callbacks. Reviewed-by: Alexander Duyck <alexanderduyck@fb.com> Reviewed-by: Jacob Keller <jacob.e.keller@intel.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
* udp_tunnel: remove REGISTER/UNREGISTER handling from tunnel driversJakub Kicinski2021-01-072-20/+9
| | | | | | | | | | udp_tunnel_nic handles REGISTER and UNREGISTER event, now that all drivers use that infra we can drop the event handling in the tunnel drivers. Reviewed-by: Alexander Duyck <alexanderduyck@fb.com> Reviewed-by: Jacob Keller <jacob.e.keller@intel.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
* net: broadcom: Drop OF dependency from BGMAC_PLATFORMFlorian Fainelli2021-01-071-1/+0
| | | | | | | | | | All of the OF code that is used has stubbed and will compile and link just fine, keeping COMPILE_TEST is enough. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Acked-by: Randy Dunlap <rdunlap@infradead.org> Link: https://lore.kernel.org/r/20210106191546.1358324-1-f.fainelli@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
* bcm63xx_enet: improve rx loopSieng Piaw Liew2021-01-071-2/+2
| | | | | | | | | | | | Use existing rx processed count to track against budget, thereby making budget decrement operation redundant. rx_desc_count can be calculated outside the rx loop, making the loop a bit smaller. Signed-off-by: Sieng Piaw Liew <liew.s.piaw@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
* bcm63xx_enet: convert to build_skbSieng Piaw Liew2021-01-072-54/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can increase the efficiency of rx path by using buffers to receive packets then build SKBs around them just before passing into the network stack. In contrast, preallocating SKBs too early reduces CPU cache efficiency. Check if we're in NAPI context when refilling RX. Normally we're almost always running in NAPI context. Dispatch to napi_alloc_frag directly instead of relying on netdev_alloc_frag which does the same but with the overhead of local_bh_disable/enable. Tested on BCM6328 320 MHz and iperf3 -M 512 to measure packet/sec performance. Included netif_receive_skb_list and NET_IP_ALIGN optimizations. Before: [ ID] Interval Transfer Bandwidth Retr [ 4] 0.00-10.00 sec 49.9 MBytes 41.9 Mbits/sec 197 sender [ 4] 0.00-10.00 sec 49.3 MBytes 41.3 Mbits/sec receiver After: [ ID] Interval Transfer Bandwidth Retr [ 4] 0.00-30.00 sec 171 MBytes 47.8 Mbits/sec 272 sender [ 4] 0.00-30.00 sec 170 MBytes 47.6 Mbits/sec receiver Signed-off-by: Sieng Piaw Liew <liew.s.piaw@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
* bcm63xx_enet: consolidate rx SKB ring cleanup codeSieng Piaw Liew2021-01-071-50/+22
| | | | | | | | | The rx SKB ring use the same code for cleanup at various points. Combine them into a function to reduce lines of code. Signed-off-by: Sieng Piaw Liew <liew.s.piaw@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
* bcm63xx_enet: alloc rx skb with NET_IP_ALIGNSieng Piaw Liew2021-01-071-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | Use netdev_alloc_skb_ip_align on newer SoCs with integrated switch (enetsw) when refilling RX. Increases packet processing performance by 30% (with netif_receive_skb_list). Non-enetsw SoCs cannot function with the extra pad so continue to use the regular netdev_alloc_skb. Tested on BCM6328 320 MHz and iperf3 -M 512 to measure packet/sec performance. Before: [ ID] Interval Transfer Bandwidth Retr [ 4] 0.00-30.00 sec 120 MBytes 33.7 Mbits/sec 277 sender [ 4] 0.00-30.00 sec 120 MBytes 33.5 Mbits/sec receiver After (+netif_receive_skb_list): [ 4] 0.00-30.00 sec 155 MBytes 43.3 Mbits/sec 354 sender [ 4] 0.00-30.00 sec 154 MBytes 43.1 Mbits/sec receiver Signed-off-by: Sieng Piaw Liew <liew.s.piaw@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
* bcm63xx_enet: add xmit_more supportSieng Piaw Liew2021-01-071-1/+2
| | | | | | | | Support bulking hardware TX queue by using netdev_xmit_more(). Signed-off-by: Sieng Piaw Liew <liew.s.piaw@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
* bcm63xx_enet: add BQL supportSieng Piaw Liew2021-01-071-0/+9
| | | | | | | | | Add Byte Queue Limits support to reduce/remove bufferbloat in bcm63xx_enet. Signed-off-by: Sieng Piaw Liew <liew.s.piaw@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
* bcm63xx_enet: batch process rx pathSieng Piaw Liew2021-01-071-1/+5
| | | | | | | | | | | | | | | | | | | | Use netif_receive_skb_list to batch process rx skb. Tested on BCM6328 320 MHz using iperf3 -M 512, increasing performance by 12.5%. Before: [ ID] Interval Transfer Bandwidth Retr [ 4] 0.00-30.00 sec 120 MBytes 33.7 Mbits/sec 277 sender [ 4] 0.00-30.00 sec 120 MBytes 33.5 Mbits/sec receiver After: [ ID] Interval Transfer Bandwidth Retr [ 4] 0.00-30.00 sec 136 MBytes 37.9 Mbits/sec 203 sender [ 4] 0.00-30.00 sec 135 MBytes 37.7 Mbits/sec receiver Signed-off-by: Sieng Piaw Liew <liew.s.piaw@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
* qmi_wwan: Increase headroom for QMAP SKBsKristian Evensen2021-01-071-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When measuring the throughput (iperf3 + TCP) while routing on a not-so-powerful device (Mediatek MT7621, 880MHz CPU), I noticed that I achieved significantly lower speeds with QMI-based modems than for example a USB LAN dongle. The CPU was saturated in all of my tests. With the dongle I got ~300 Mbit/s, while I only measured ~200 Mbit/s with the modems. All offloads, etc. were switched off for the dongle, and I configured the modems to use QMAP (16k aggregation). The tests with the dongle were performed in my local (gigabit) network, while the LTE network the modems were connected to delivers 700-800 Mbit/s. Profiling the kernel revealed the cause of the performance difference. In qmimux_rx_fixup(), an SKB is allocated for each packet contained in the URB. This SKB has too little headroom, causing the check in skb_cow() (called from ip_forward()) to fail. pskb_expand_head() is then called and the SKB is reallocated. In the output from perf, I see that a significant amount of time is spent in pskb_expand_head() + support functions. In order to ensure that the SKB has enough headroom, this commit increases the amount of memory allocated in qmimux_rx_fixup() by LL_MAX_HEADER. The reason for using LL_MAX_HEADER and not a more accurate value, is that we do not know the type of the outgoing network interface. After making this change, I achieve the same throughput with the modems as with the dongle. Signed-off-by: Kristian Evensen <kristian.evensen@gmail.com> Acked-by: Bjørn Mork <bjorn@mork.no> Link: https://lore.kernel.org/r/20210106122403.1321180-1-kristian.evensen@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
* can: flexcan: add CAN wakeup function for i.MX8QMJoakim Zhang2021-01-061-17/+106
| | | | | | | | | | | | | | | | The System Controller Firmware (SCFW) is a low-level system function which runs on a dedicated Cortex-M core to provide power, clock, and resource management. It exists on some i.MX8 processors. e.g. i.MX8QM (QM, QP), and i.MX8QX (QXP, DX). SCU driver manages the IPC interface between host CPU and the SCU firmware running on M4. For i.MX8QM, stop mode request is controlled by System Controller Unit(SCU) firmware, this patch introduces FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW quirk for this function. Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com> Link: https://lore.kernel.org/r/20201106105627.31061-6-qiangqing.zhang@nxp.com Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
* can: tcan4x5x: add support for half-duplex controllersMarc Kleine-Budde2021-01-061-6/+15
| | | | | | | | | | This patch adds back support for half-duplex controllers, which was removed in the last patch. Reviewed-by: Dan Murphy <dmurphy@ti.com> Tested-by: Sean Nyekjaer <sean@geanix.com> Link: https://lore.kernel.org/r/20201215231746.1132907-17-mkl@pengutronix.de Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
* can: tcan4x5x: rework SPI accessMarc Kleine-Budde2021-01-063-28/+84
| | | | | | | | | | | | | | | | | | | | | | | This patch reworks the SPI access and fixes several probems: - tcan4x5x_regmap_gather_write(), tcan4x5x_regmap_read(): Do not place variable "addr" on stack and use it as buffer for SPI transfer. Buffers for SPI transfers must be allocated from DMA save memory. - tcan4x5x_regmap_gather_write(), tcan4x5x_regmap_read(): Halfe number of SPI transfers by using a single buffer + memcpy(). This improves the performance, especially on SPI controllers, which use interrupt based transfers. - Use "8" bits per word, not "32". This makes it possible to use this driver on SoCs like the Raspberry Pi, which SPI host controller drivers only support 8 bits per word. Note: this breaks half duplex only controllers. Support for them will be re-added in the next patch. Reviewed-by: Dan Murphy <dmurphy@ti.com> Tested-by: Sean Nyekjaer <sean@geanix.com> Link: https://lore.kernel.org/r/20201215231746.1132907-16-mkl@pengutronix.de Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
* can: tcan4x5x: add {wr,rd}_tableMarc Kleine-Budde2021-01-061-0/+14
| | | | | | | | | | The memory space of the chip is not fully populated, so add a regmap range table to document this. Reviewed-by: Dan Murphy <dmurphy@ti.com> Tested-by: Sean Nyekjaer <sean@geanix.com> Link: https://lore.kernel.org/r/20201215231746.1132907-15-mkl@pengutronix.de Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
* can: tcan4x5x: add max_raw_{read,write} of 256Marc Kleine-Budde2021-01-061-0/+2
| | | | | | | | | | The tcan4x5x chip support bulk read/write, but as the length field is only 8 bits wide, the maximum is 256. A length of 0 is treated as 256. Reviewed-by: Dan Murphy <dmurphy@ti.com> Tested-by: Sean Nyekjaer <sean@geanix.com> Link: https://lore.kernel.org/r/20201215231746.1132907-14-mkl@pengutronix.de Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
* can: tcan4x5x: tcan4x5x_regmap: set reg_stride to 4Marc Kleine-Budde2021-01-061-0/+1
| | | | | | | | | | This patch sets the regmap stide to 4, as the chip only supports access on 32 bit alligned access. Reviewed-by: Dan Murphy <dmurphy@ti.com> Tested-by: Sean Nyekjaer <sean@geanix.com> Link: https://lore.kernel.org/r/20201215231746.1132907-13-mkl@pengutronix.de Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
* can: tcan4x5x: fix max register valueMarc Kleine-Budde2021-01-061-1/+1
| | | | | | | | | This patch fixes the max register value for the regmap. Reviewed-by: Dan Murphy <dmurphy@ti.com> Tested-by: Sean Nyekjaer <sean@geanix.com> Link: https://lore.kernel.org/r/20201215231746.1132907-12-mkl@pengutronix.de Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
* can: tcan4x5x: tcan4x5x_regmap_init(): use spi as context pointerMarc Kleine-Budde2021-01-061-5/+3
| | | | | | | | | | | This patch replaces the context pointer of the regmap callback functions by a pointer to the spi_device. This saves one level of indirection in the callbacks. Reviewed-by: Dan Murphy <dmurphy@ti.com> Tested-by: Sean Nyekjaer <sean@geanix.com> Link: https://lore.kernel.org/r/20201215231746.1132907-11-mkl@pengutronix.de Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
* can: tcan4x5x: tcan4x5x_regmap_write(): remove not needed casts and replace ↵Marc Kleine-Budde2021-01-061-4/+3
| | | | | | | | | | | | 4 by sizeof This patch simplifies the tcan4x5x_regmap_write(0 function by removing not needed casts and replaces hardcoded "4" by appropriate sizeof()s. Reviewed-by: Dan Murphy <dmurphy@ti.com> Tested-by: Sean Nyekjaer <sean@geanix.com> Link: https://lore.kernel.org/r/20201215231746.1132907-10-mkl@pengutronix.de Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
* can: tcan4x5x: rename regmap_spi_gather_write() -> ↵Marc Kleine-Budde2021-01-061-5/+5
| | | | | | | | | | | | | tcan4x5x_regmap_gather_write() This patch renames the regmap_spi_gather_write() function to tcan4x5x_regmap_gather_write(). Now it has a "tcan4x5x_" prefix as all other functions in this driver. Reviewed-by: Dan Murphy <dmurphy@ti.com> Tested-by: Sean Nyekjaer <sean@geanix.com> Link: https://lore.kernel.org/r/20201215231746.1132907-9-mkl@pengutronix.de Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
* can: tcan4x5x: remove regmap async supportMarc Kleine-Budde2021-01-061-15/+0
| | | | | | | | | The driver doesn't use regmap async support, so remove the stubs. Reviewed-by: Dan Murphy <dmurphy@ti.com> Tested-by: Sean Nyekjaer <sean@geanix.com> Link: https://lore.kernel.org/r/20201215231746.1132907-8-mkl@pengutronix.de Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
* can: tcan4x5x: tcan4x5x_bus: remove not needed read_flag_maskMarc Kleine-Budde2021-01-061-1/+0
| | | | | | | | | | With C99 initializers, all non mentioned members are initialzied to 0, so remove not needed initialization of read_flag_mask. Reviewed-by: Dan Murphy <dmurphy@ti.com> Tested-by: Sean Nyekjaer <sean@geanix.com> Link: https://lore.kernel.org/r/20201215231746.1132907-7-mkl@pengutronix.de Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
* can: tcan4x5x: mark struct regmap_bus tcan4x5x_bus as constantMarc Kleine-Budde2021-01-061-1/+1
| | | | | | | | | This patch marks the struct regmap_bus tcan4x5x_bus as constant. Reviewed-by: Dan Murphy <dmurphy@ti.com> Tested-by: Sean Nyekjaer <sean@geanix.com> Link: https://lore.kernel.org/r/20201215231746.1132907-6-mkl@pengutronix.de Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
* can: tcan4x5x: move regmap code into seperate fileMarc Kleine-Budde2021-01-064-101/+133
| | | | | | | | | This patch moves the regmap code into a seperate file. Reviewed-by: Dan Murphy <dmurphy@ti.com> Tested-by: Sean Nyekjaer <sean@geanix.com> Link: https://lore.kernel.org/r/20201215231746.1132907-5-mkl@pengutronix.de Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
* can: tcan4x5x: rename tcan4x5x.c -> tcan4x5x-core.cMarc Kleine-Budde2021-01-062-0/+3
| | | | | | | | | | This is a preparation patch to move the regmap related code into a seperate file. This patch removes the tcan4x5x.c to tcan4x5x-core.c. Reviewed-by: Dan Murphy <dmurphy@ti.com> Tested-by: Sean Nyekjaer <sean@geanix.com> Link: https://lore.kernel.org/r/20201215231746.1132907-4-mkl@pengutronix.de Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
* can: tcan4x5x: beautify indention of tcan4x5x_of_match and tcan4x5x_id_tableMarc Kleine-Budde2021-01-061-5/+8
| | | | | | | | | | This patch beautifies the indention of the tcan4x5x_of_match and tcan4x5x_id_table. Reviewed-by: Dan Murphy <dmurphy@ti.com> Tested-by: Sean Nyekjaer <sean@geanix.com> Link: https://lore.kernel.org/r/20201215231746.1132907-3-mkl@pengutronix.de Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
* can: tcan4x5x: replace DEVICE_NAME by KBUILD_MODNAMEMarc Kleine-Budde2021-01-061-4/+3
| | | | | | | | | | This patch replaces the DEVICE_NAME macro by KBUILD_MODNAME and removed the superfluous DEVICE_NAME. Reviewed-by: Dan Murphy <dmurphy@ti.com> Tested-by: Sean Nyekjaer <sean@geanix.com> Link: https://lore.kernel.org/r/20201215231746.1132907-2-mkl@pengutronix.de Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
* net: ks8851: Register MDIO bus and the internal PHYMarek Vasut2021-01-052-16/+98
| | | | | | | | | | | | | | The KS8851 has a reduced internal PHY, which is accessible through its registers at offset 0xe4. The PHY is compatible with KS886x PHY present in Micrel switches, except the PHY ID Low/High registers are swapped. Register MDIO bus so this PHY can be detected and probed by phylib. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Heiner Kallweit <hkallweit1@gmail.com> Cc: Lukas Wunner <lukas@wunner.de> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: phy: micrel: Add KS8851 PHY supportMarek Vasut2021-01-051-1/+1
| | | | | | | | | | | | | | The KS8851 has a reduced internal PHY, which is accessible through its registers at offset 0xe4. The PHY is compatible with KS886x PHY present in Micrel switches, including the PHY ID Low/High registers swap, which is present both in the MAC and the switch. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Heiner Kallweit <hkallweit1@gmail.com> Cc: Lukas Wunner <lukas@wunner.de> Signed-off-by: David S. Miller <davem@davemloft.net>
* macvlan: remove redundant null check on dataYunjian Wang2021-01-051-1/+1
| | | | | | | | | | Because macvlan_common_newlink() and macvlan_changelink() already checked NULL data parameter, so the additional check is unnecessary, just remove it. Fixes: 79cf79abce71 ("macvlan: add source mode") Signed-off-by: Yunjian Wang <wangyunjian@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* octeontx2-pf: Add RSS multi group supportGeetha sowjanya2021-01-054-44/+163
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hardware supports 8 RSS groups per interface. Currently we are using only group '0'. This patch allows user to create new RSS groups/contexts and use the same as destination for flow steering rules. usage: To steer the traffic to RQ 2,3 ethtool -X eth0 weight 0 0 1 1 context new (It will print the allocated context id number) New RSS context is 1 ethtool -N eth0 flow-type tcp4 dst-port 80 context 1 loc 1 To delete the context ethtool -X eth0 context 1 delete When an RSS context is removed, the active classification rules using this context are also removed. Change-log: v4 - Fixed compiletime warning. - Address Saeed's comments on v3. v3 - Coverted otx2_set_rxfh() to use new function. v2 - Removed unrelated whitespace - Coverted otx2_get_rxfh() to use new function. Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com> Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* net/mlxfw: Use kzalloc for allocating only one thingZheng Yongjun2021-01-051-1/+1
| | | | | | | | | | | | | | | | | | | | Use kzalloc rather than kcalloc(1,...) The semantic patch that makes this change is as follows: (http://coccinelle.lip6.fr/) // <smpl> @@ @@ - kcalloc(1, + kzalloc( ...) // </smpl> Signed-off-by: Zheng Yongjun <zhengyongjun3@huawei.com> Reviewed-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* Merge tag 'mlx5-updates-2021-01-05' of ↵David S. Miller2021-01-0510-2078/+2329
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux Saeed Mahameed says: ==================== mlx5-updates-2021-01-05 SW steering, Refactor to have a device specific STE layer below dr_ste This series introduces some improvements and refactoring by adding a new layer below dr_ste to allow support for different devices format. It adds a struct of device specific callbacks for STE layer below dr_ste. Each device will implement its HW-specific function, and a common logic from the DR code will access these functions through the new ste_ctx API. Connect-X5-style steering format is called STE_v0. In the next patch series we bring the Connect-X6-style format - STE_v1. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
| * net/mlx5: DR, Move STEv0 modify header logicYevgeny Kliteynik2021-01-056-390/+501
| | | | | | | | | | | | | | | | | | | | | | | | Move HW specific modify header fields and logic to STEv0 file and use the new STE context callbacks. Since STEv0 and STEv1 modify actions values are different, each version has its own implementation. Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Alex Vesker <valex@nvidia.com> Reviewed-by: Saeed Mahameed <saeedm@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
| * net/mlx5: DR, Add STE modify header actions per-device APIYevgeny Kliteynik2021-01-051-0/+23
| | | | | | | | | | | | | | | | Extend the STE context struct with per-device modify header actions. Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Saeed Mahameed <saeedm@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
| * net/mlx5: DR, Move STEv0 action apply logicYevgeny Kliteynik2021-01-052-235/+256
| | | | | | | | | | | | | | | | | | | | | | | | Use STE tx/rx actions per-device API: move HW specific action apply logic from dr_ste to STEv0 file - STEv0 and STEv1 actions format is different, each version should have its own implementation. Signed-off-by: Alex Vesker <valex@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Saeed Mahameed <saeedm@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
| * net/mlx5: DR, Add STE tx/rx actions per-device APIYevgeny Kliteynik2021-01-051-0/+12
| | | | | | | | | | | | | | | | | | Extend the STE context struct with per-device tx/rx actions. Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Saeed Mahameed <saeedm@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
| * net/mlx5: DR, Move STEv0 setters and gettersYevgeny Kliteynik2021-01-055-103/+195
| | | | | | | | | | | | | | | | | | | | | | | | Use the new setters and getters API for STEv0: move HW specific setter and getters from dr_ste to STEv0 file. Since STEv0 and STEv1 format are different each version should implemented different setters and getters. Rename remaining static functions w/o mlx5 prefix. Signed-off-by: Alex Vesker <valex@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Saeed Mahameed <saeedm@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
| * net/mlx5: DR, Add STE setters and getters per-device APIYevgeny Kliteynik2021-01-051-0/+12
| | | | | | | | | | | | | | | | | | Extend the STE context struct with various per-device setters and getters. Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Saeed Mahameed <saeedm@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
| * net/mlx5: DR, Move action apply logic to dr_steYevgeny Kliteynik2021-01-053-234/+231
| | | | | | | | | | | | | | | | | | | | | | The action apply logic is device specific per STE version, moving to the STE layer will allow implementing it for both devices while keeping DR upper layers the same. Signed-off-by: Alex Vesker <valex@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Saeed Mahameed <saeedm@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
| * net/mlx5: DR, Refactor ICMP STE builderYevgeny Kliteynik2021-01-052-42/+23
| | | | | | | | | | | | | | | | | | | | | | Reworked ICMP tag builder to better handle ICMP v4/6 fields and avoid unneeded code duplication and 'if' statements, removed unused macro, changed bitfield of len 8 to u8. Signed-off-by: Alex Vesker <valex@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Saeed Mahameed <saeedm@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
| * net/mlx5: DR, Move STEv0 look up types from mlx5_ifc_dr headerYevgeny Kliteynik2021-01-054-60/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | The lookup types are device specific and should not be exposed to DR upper layers, matchers/tables. Each HW STE version should keep them internal. The lu_type size is updated to support larger lu_types as required for STEv1. Signed-off-by: Alex Vesker <valex@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Saeed Mahameed <saeedm@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
| * net/mlx5: DR, Merge similar DR STE SET macrosYevgeny Kliteynik2021-01-052-415/+84
| | | | | | | | | | | | | | | | | | | | | | | | Merge DR_STE_STE macros for better code reuse, the macro DR_STE_SET_MASK_V and DR_STE_SET_TAG are merged to avoid tag and bit_mask function creation which are usually the same. Signed-off-by: Alex Vesker <valex@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Saeed Mahameed <saeedm@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
| * net/mlx5: DR, Fix STEv0 source_eswitch_owner_vhca_id supportYevgeny Kliteynik2021-01-051-11/+14
| | | | | | | | | | | | | | | | | | Check vport_cap only if match on source gvmi is required. Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Alex Vesker <valex@nvidia.com> Reviewed-by: Saeed Mahameed <saeedm@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
| * net/mlx5: DR, Remove unused macro definition from dr_steYevgeny Kliteynik2021-01-051-2/+0
| | | | | | | | | | | | Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Saeed Mahameed <saeedm@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
| * net/mlx5: DR, Move HW STEv0 match logic to a separate fileYevgeny Kliteynik2021-01-054-1279/+1286
| | | | | | | | | | | | | | | | | | | | | | | | Move current STE match logic to a seprate file. This file will be used for HW specific STEv0. Future patches will add functionality for v1 steering. Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Alex Vesker <valex@nvidia.com> Reviewed-by: Saeed Mahameed <saeedm@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
| * net/mlx5: DR, Use the new HW specific STE infrastructureYevgeny Kliteynik2021-01-055-330/+613
| | | | | | | | | | | | | | | | | | | | | | | | | | Split the STE builders functionality into the common part and device-specific part. All the device-specific part (with 'v0' in the function names) is accessed through the STE context structure. Subsequent patches will have the device-specific logic moved to a separate file. Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Saeed Mahameed <saeedm@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
| * net/mlx5: DR, Move macros from dr_ste.c to headerYevgeny Kliteynik2021-01-052-74/+76
| | | | | | | | | | | | | | | | | | Move some macros from dr_ste.c to header - these macros will be used by all the format-specific functions. Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Saeed Mahameed <saeedm@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
| * net/mlx5: DR, Add infrastructure for supporting several steering formatsYevgeny Kliteynik2021-01-052-1/+37
| | | | | | | | | | | | | | | | | | | | | | | | Add a struct of device specific callbacks for STE layer below dr_ste. Each device will implement its HW-specific function, and a comon logic from the DR code will access these functions through the new ste_ctx API. More callbacks will follow in the subsequent patches. Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Saeed Mahameed <saeedm@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-18 15:34:28 +0000