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Add read_s function in cmdq helper functions which support read value from
register or dma physical address into gce internal register.
Signed-off-by: Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com>
Link: https://lore.kernel.org/r/1594136714-11650-5-git-send-email-dennis-yc.hsieh@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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add write_s_mask function in cmdq helper functions which
writes value contains in internal register to address
with mask and large dma access support.
Signed-off-by: Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com>
Link: https://lore.kernel.org/r/1594136714-11650-4-git-send-email-dennis-yc.hsieh@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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add write_s function in cmdq helper functions which
writes value contains in internal register to address
with large dma access support.
Signed-off-by: Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com>
Link: https://lore.kernel.org/r/1594136714-11650-3-git-send-email-dennis-yc.hsieh@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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arm/drivers
Reset controller updates for v5.10
This tag allows to build reset-imx7 as a module, and adds support to
reset the Cortex-M4 processor on i.MX8MQ to it, adds support for the
Versal platform to the reset-zynqmp driver, and fixes some kerneldoc
comments in the core and in sti/reset-syscfg.
* tag 'reset-for-v5.10' of git://git.pengutronix.de/pza/linux:
reset: sti: reset-syscfg: fix struct description warnings
reset: imx7: add the cm4 reset for i.MX8MQ
dt-bindings: reset: imx8mq: add m4 reset
reset: Fix and extend kerneldoc
reset: reset-zynqmp: Added support for Versal platform
dt-bindings: reset: Updated binding for Versal reset driver
reset: imx7: Support module build
Link: https://lore.kernel.org/r/2b77c90d2b970eb8fa09000b9ecb564bffa76374.camel@pengutronix.de
Signed-off-by: Olof Johansson <olof@lixom.net>
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Add the m4 reset used by the remoteproc driver
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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Added documentation and Versal reset indices to describe
about Versal reset driver bindings.
In Versal all reset indices includes Class, SubClass, Type, Index
information whereas class refers to clock, reset, power etc.,
Underlying firmware in Versal have such classification and expects
the ID to be this way.
[13:0] - Index bits
[19:14] - Type bits
[25:20] - SubClass bits
[31:26] - Class bits.
Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/drivers
soc: amlogic: driver updates for v5.10
- misc. pm-domain updates
* tag 'amlogic-drivers' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
soc: amlogic: pm-domains: use always-on flag
soc: amlogic: meson-ee-pwrc: add support for the Meson AXG SoCs
dt-bindings: power: amlogic, meson-ee-pwrc: add Amlogic AXG power controller bindings
Link: https://lore.kernel.org/r/7hblhukjzx.fsf@baylibre.com
Signed-off-by: Olof Johansson <olof@lixom.net>
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bindings
This add the bindings of the Power Controller found in the Amlogic AXG SoCs.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20200917064702.1459-2-narmstrong@baylibre.com
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https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/drivers
Qualcomm driver updates for v5.10
Replace the busy wait for free tcs slots in the RPMh driver with a
sleeping wait and use memory barriers when writing the command registers.
Add a bunch of SoC ids to the socinfo driver, fix an erro printin the
apr driver and migrate llcc to devm_platform_ioremap_resource_byname().
* tag 'qcom-drivers-for-5.10' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
soc: qcom: llcc: use devm_platform_ioremap_resource_byname()
soc: qcom: apr: Fixup the error displayed on lookup failure
soc: qcom: socinfo: Add msm8992/4 and apq8094 SoC IDs
soc: qcom: rpmh-rsc: Sleep waiting for tcs slots to be free
soc: qcom-geni-se: Don't use relaxed writes when writing commands
soc: qcom: socinfo: add SC7180 entry to soc_id array
soc: qcom: socinfo: add soc id for IPQ6018
Link: https://lore.kernel.org/r/20200924040504.179708-1-bjorn.andersson@linaro.org
Signed-off-by: Olof Johansson <olof@lixom.net>
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Writing the command is the final step in kicking off a transfer.
Let's use writel() to ensure that any other memory accesses are done
before the command kicks off. It's expected that this is mostly
relevant if we're in DMA mode but since it doesn't appear to regress
performance in a measurable way [1] even in PIO mode and it's easier
to reason about then let's just always use it.
NOTE: this patch came about due to code inspection. No actual
problems were observed that this patch fixes.
[1] Tested by timing "flashrom -p ec" on a Chromebook which stresses
GENI SPI a lot.
Reviewed-by: Mukesh Kumar Savaliya <msavaliy@codeaurora.org>
Reviewed-by: Akash Asthana <akashast@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Suggested-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20200722150113.1.Ia50ab5cb8a6d3a73d302e6bdc25542d48ffd27f4@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux into arm/drivers
NXP/FSL SoC driver updates for v5.10
Fix various compile warnings and static analysis warnings for:
- QBMan driver
- DPIO driver
- QE driver
* tag 'soc-fsl-next-v5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux:
soc: fsl: qe: Remove unnessesary check in ucc_set_tdm_rxtx_clk
soc: fsl: qman: convert to use be32_add_cpu()
soc: fsl: dpio: remove set but not used 'addr_cena'
soc: fsl: qbman: Fix return value on success
soc: fsl: qman: fix -Wpacked-not-aligned warnings
Link: https://lore.kernel.org/r/20200923224416.25788-1-leoyang.li@nxp.com
Signed-off-by: Olof Johansson <olof@lixom.net>
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This fixes compile warnings from the -Wpacked-not-aligned option.
In file included from ../drivers/crypto/caam/qi.c:12:
../include/soc/fsl/qman.h:259:1: warning: alignment 1 of ‘struct qm_dqrr_entry’ is less than 8 [-Wpacked-not-aligned]
} __packed;
^
../include/soc/fsl/qman.h:292:2: warning: alignment 1 of ‘struct <anonymous>’ is less than 8 [-Wpacked-not-aligned]
} __packed ern;
^
Reported-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into arm/drivers
ARM: soc: TI driver updates for v5.10
Consist of:
- Add Ring accelerator support for AM65x
- Add TI PRUSS platform driver and enable it on available platforms
- Extend PRUSS driver for CORECLK_MUX/IEPCLK_MUX support
- UDMA rx ring pair fix
- Add socinfo entry for J7200
* tag 'drivers_soc_for_5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone:
Add missing '#' to fix schema errors:
soc: ti: Convert to DEFINE_SHOW_ATTRIBUTE
dmaengine: ti: k3-udma-glue: Fix parameters for rx ring pair request
soc: ti: k3-socinfo: Add entry for J7200
soc: ti: pruss: support CORECLK_MUX and IEPCLK_MUX
dt-bindings: soc: ti: Update TI PRUSS bindings regarding clock-muxes
firmware: ti_sci: allow frequency change for disabled clocks by default
soc: ti: ti_sci_pm_domains: switch to use multiple genpds instead of one
soc: ti: pruss: Enable support for ICSSG subsystems on K3 J721E SoCs
soc: ti: pruss: Enable support for ICSSG subsystems on K3 AM65x SoCs
soc: ti: pruss: Add support for PRU-ICSS subsystems on 66AK2G SoC
soc: ti: pruss: Add support for PRU-ICSS subsystems on AM57xx SoCs
soc: ti: pruss: Add support for PRU-ICSSs on AM437x SoCs
soc: ti: pruss: Add a platform driver for PRUSS in TI SoCs
dt-bindings: soc: ti: Add TI PRUSS bindings
bindings: soc: ti: soc: ringacc: remove ti,dma-ring-reset-quirk
soc: ti: k3: ringacc: add am65x sr2.0 support
Link: https://lore.kernel.org/r/1600656828-29267-1-git-send-email-santosh.shilimkar@oracle.com
Signed-off-by: Olof Johansson <olof@lixom.net>
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The IEPCLK_MUX is present on all SoCs whereas the CORECLK_MUX is present
only on AM65x SoCs and J721E. Add support for both these CLK muxes.
This allows the clock rates and clock parents for these to be controlled
through DT leveraging the clk infrastructure for configuring the default
parents and rates.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
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The Programmable Real-Time Unit - Industrial Communication
Subsystem (PRU-ICSS) is present on various TI SoCs such as
AM335x or AM437x or the Keystone 66AK2G. Each SoC can have
one or more PRUSS instances that may or may not be identical.
For example, AM335x SoCs have a single PRUSS, while AM437x has
two PRUSS instances PRUSS1 and PRUSS0, with the PRUSS0 being
a cut-down version of the PRUSS1.
The PRUSS consists of dual 32-bit RISC cores called the
Programmable Real-Time Units (PRUs), some shared, data and
instruction memories, some internal peripheral modules, and
an interrupt controller. The programmable nature of the PRUs
provide flexibility to implement custom peripheral interfaces,
fast real-time responses, or specialized data handling.
The PRU-ICSS functionality is achieved through three different
platform drivers addressing a specific portion of the PRUSS.
Some sub-modules of the PRU-ICSS IP reuse some of the existing
drivers (like davinci mdio driver or the generic syscon driver).
This design provides flexibility in representing the different
modules of PRUSS accordingly, and at the same time allowing the
PRUSS driver to add some instance specific configuration within
an SoC.
The PRUSS platform driver deals with the overall PRUSS and is
used for managing the subsystem level resources like various
memories and the CFG module. It is responsible for the creation
and deletion of the platform devices for the child PRU devices
and other child devices (like Interrupt Controller, MDIO node
and some syscon nodes) so that they can be managed by specific
platform drivers. The PRUSS interrupt controller is managed by
an irqchip driver, while the individual PRU RISC cores are
managed by a PRU remoteproc driver.
The driver currently supports the AM335x SoC, and support for
other TI SoCs will be added in subsequent patches.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers
soc/tegra: Changes for v5.10-rc1
These changes contain a bit of cleanup and chip support for the upcoming
Tegra234 SoC.
* tag 'tegra-for-5.10-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
soc/tegra: pmc: Add Tegra234 support
soc/tegra: pmc: Reorder reset sources/levels definitions
soc/tegra: misc: Add Tegra234 support
soc/tegra: fuse: Add Tegra234 support
soc/tegra: fuse: Implement tegra_is_silicon()
soc/tegra: fuse: Extract tegra_get_platform()
Link: https://lore.kernel.org/r/20200918150303.3938852-2-thierry.reding@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
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Add support for FUSE block found on the Tegra234 SoC, which is largely
similar to the IP found on previous generations.
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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This function can be used by drivers to determine whether code is
running on silicon or on a simulation platform.
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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This function extracts the PRE_SI_PLATFORM field from the HIDREV
register and can be used to determine which platform the kernel runs on
(silicon, simulation, ...). Note that while only Tegra194 and later
define this field, it should be safe to call this on prior generations
as well since this field should read as 0, indicating silicon.
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/drivers
Renesas driver updates for v5.10 (take two)
- Add core support for the R-Car V3U (R8A779A0) SoC, including System
Controller (SYSC) and Reset (RST) support,
- Various Kconfig cleanups.
* tag 'renesas-drivers-for-v5.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
soc: renesas: r8a779a0-sysc: Add r8a779a0 support
soc: renesas: rcar-rst: Add support for R-Car V3U
soc: renesas: Identify R-Car V3U
soc: renesas: Sort driver description title
soc: renesas: Use ARM32/ARM64 for menu description
dt-bindings: clock: Add r8a779a0 CPG Core Clock Definitions
dt-bindings: power: Add r8a779a0 SYSC power domain definitions
Link: https://lore.kernel.org/r/20200918124800.15555-4-geert+renesas@glider.be
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/drivers
ARM SCMI updates for v5.10
Couple of main additions: SCMI system protocol support and ability to
build SCMI driver as a single module which is needed by some transports
like virtio as they may not be ready early during the boot. This also
includes constification of scmi ops and related function pointers.
* tag 'scmi-updates-5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
firmware: arm_scmi: Enable building as a single module
firmware: arm_scmi: Move scmi protocols registration into the driver
firmware: arm_scmi: Move scmi bus init and exit calls into the driver
firmware: smccc: Export both smccc functions
firmware: arm_scmi: Fix NULL pointer dereference in mailbox_chan_free
firmware: arm_scmi: Add SCMI device for system power protocol
firmware: arm_scmi: Add system power protocol support
firmware: arm_scmi: Constify static scmi-ops
firmware: arm_scmi: Constify ops pointers in scmi_handle
cpufreq: arm_scmi: Constify scmi_perf_ops pointers
Link: https://lore.kernel.org/r/20200914075018.2rvytvghxyutcbk4@bogus
Signed-off-by: Olof Johansson <olof@lixom.net>
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Now, with all the plumbing in place to enable building scmi as a module
instead of built-in modules, let us enable the same.
Link: https://lore.kernel.org/r/20200907195046.56615-5-sudeep.holla@arm.com
Tested-by: Cristian Marussi <cristian.marussi@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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Add bare protocol support for SCMI system power protocol as needed by
an OSPM agent: basic initialization and SYSTEM_POWER_STATE_NOTIFIER
core notification support.
No event-handling logic is attached to such notification..
Link: https://lore.kernel.org/r/20200907174657.32466-2-cristian.marussi@arm.com
Signed-off-by: Cristian Marussi <cristian.marussi@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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These are never modified, so make them const to allow drivers to make
them const.
Link: https://lore.kernel.org/r/20200906230452.33410-3-rikard.falkeborn@gmail.com
Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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into arm/drivers
This pull request contains Broadcom SoCs drivers changes for 5.10,
please pull the following:
- Alvaro adds support for the BCM63xx (DSL) SoCs power domain controller
and adds support for the 6318, 6328, 6362, 63268.
- Florian adds support for tuning the Bus Interface Unit on 72164 and
72165, enables the Brahma-B53 and Cortex-A72 read-ahead cache for the
64-bit capable ARCH_BRCMSTB platforms, and finally updates the GISB
driver to support breakpoint notifications.
* tag 'arm-soc/for-5.10/drivers' of https://github.com/Broadcom/stblinux:
bus: brcmstb_gisb: Add support for breakpoint interrupts
dt-bindings: bus: Document breakpoint interrupt for gisb-arb
soc: bcm: brcmstb: biuctrl: Change RAC data line prefetching after 4 consecutive lines
soc: bcm: brcmstb: biuctrl: Change RAC prefetch distance from +/-1 to +/- 2
soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72165
soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72164
MIPS: BMIPS: dts: add BCM63268 power domain support
MIPS: BMIPS: dts: add BCM6362 power domain support
MIPS: BMIPS: dts: add BCM6328 power domain support
soc: bcm: add BCM63xx power domain driver
MIPS: BMIPS: add BCM6318 power domain definitions
MIPS: BMIPS: add BCM63268 power domain definitions
MIPS: BMIPS: add BCM6362 power domain definitions
MIPS: BMIPS: add BCM6328 power domain definitions
dt-bindings: soc: brcm: add BCM63xx power domain binding
soc: bcm: brcmstb: biuctrl: Enable Read-ahead cache
bus: brcmstb_gisb: Shorten prints
Link: https://lore.kernel.org/r/20200912032153.1216354-3-f.fainelli@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
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BCM6318 SoCs have a power domain controller to enable/disable certain
components in order to save power.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Florian Fainelli <F.fainelli@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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BCM63268 SoCs have a power domain controller to enable/disable certain
components in order to save power.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Florian Fainelli <F.fainelli@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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BCM6362 SoCs have a power domain controller to enable/disable certain
components in order to save power.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Florian Fainelli <F.fainelli@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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BCM6328 SoCs have a power domain controller to enable/disable certain
components in order to save power.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Florian Fainelli <F.fainelli@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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TEE Client introduce a new capability "TEE_GEN_CAP_MEMREF_NULL"
to handle the support of the shared memory buffer with a NULL pointer.
This capability depends on TEE Capabilities and driver support.
Driver and TEE exchange capabilities at driver initialization.
Signed-off-by: Michael Whitfield <michael.whitfield@nxp.com>
Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Tested-by: Joakim Bech <joakim.bech@linaro.org> (QEMU)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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Pull ARM SoC platform updates from Olof Johansson:
"SoC changes, a substantial part of this is cleanup of some of the
older platforms that used to have a bunch of board files.
In particular:
- Remove non-DT i.MX platforms that haven't seen activity in years,
it's time to remove them.
- A bunch of cleanup and removal of platform data for TI/OMAP
platforms, moving over to genpd for power/reset control (yay!)
- Major cleanup of Samsung S3C24xx and S3C64xx platforms, moving them
closer to multiplatform support (not quite there yet, but getting
close).
There are a few other changes too, smaller fixlets, etc. For new
platform support, the primary ones are:
- New SoC: Hisilicon SD5203, ARM926EJ-S platform.
- Cpufreq support for i.MX7ULP"
* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (121 commits)
ARM: mstar: Select MStar intc
ARM: stm32: Replace HTTP links with HTTPS ones
ARM: debug: add UART early console support for SD5203
ARM: hisi: add support for SD5203 SoC
ARM: omap3: enable off mode automatically
clk: imx: imx35: Remove mx35_clocks_init()
clk: imx: imx31: Remove mx31_clocks_init()
clk: imx: imx27: Remove mx27_clocks_init()
ARM: imx: Remove unused definitions
ARM: imx35: Retrieve the IIM base address from devicetree
ARM: imx3: Retrieve the AVIC base address from devicetree
ARM: imx3: Retrieve the CCM base address from devicetree
ARM: imx31: Retrieve the IIM base address from devicetree
ARM: imx27: Retrieve the CCM base address from devicetree
ARM: imx27: Retrieve the SYSCTRL base address from devicetree
ARM: s3c64xx: bring back notes from removed debug-macro.S
ARM: s3c24xx: fix Wunused-variable warning on !MMU
ARM: samsung: fix PM debug build with DEBUG_LL but !MMU
MAINTAINERS: mark linux-samsung-soc list non-moderated
ARM: imx: Remove remnant board file support pieces
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git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/soc
Add initial genpd support for omaps to drop more platform data
We now drop legacy platform data for RTC on am3, am4 and dra7.
And we add initial genpd support for PRM (Power and Reset Manager)
and use it to drop legacy platform data for am3 sgx and omap4/5
l4_abe interconnect instance.
* tag 'omap-for-v5.10/ti-sysc-drop-pdata-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: Drop legacy platform data for dra7 rtcss
ARM: OMAP2+: Drop legacy platform data for am3 and am4 rtc
soc: ti: pm33xx: Simplify RTC usage to prepare to drop platform data
ARM: dts: Configure omap4 and 5 l4_abe for genpd and drop platform data
ARM: dts: Configure am3 and am4 sgx for genpd and drop platform data
soc: ti: omap-prm: Configure omap4 and 5 l4_abe power domain
soc: ti: omap-prm: Configure sgx power domain for am3 and am4
soc: ti: omap-prm: Add basic power domain support
dt-bindings: omap: Update PRM binding for genpd
Link: https://lore.kernel.org/r/pull-1599132307-761202@atomide.com-2
Signed-off-by: Olof Johansson <olof@lixom.net>
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We must re-enable the RTC module clock enabled in RTC+DDR suspend, and
pm33xx has been using platform data callbacks for that. Looks like for
retention suspend the RTC module clock must not be re-enabled.
To remove the legacy platform data callbacks, and eventually be able to
drop the RTC legacy platform data, let's manage the RTC module clock
and register range directly in pm33xx.
Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/soc
Samsung S3C24xx and S3C64xx machine code cleanup for v5.10
Big cleanup for the Samsung S3C24xx and S3C64xx platforms, although it
also touches files shared with S5Pv210 and Exynos. This is mostly Arnd
Bergmann work which Krzysztof Kozlowski took over, rebased and polished.
The goal is to cleanup, merge and finally make the Samsung S3C24xx and
S3C64xx architectures multiplatform. The multiplatform did not happen
yet here - just cleaning up and merging into one arch/arm/mach-s3c
directory. However this is step forward for multiplatform or at least
to keep this code still maintainable.
This pulls also branch with changes for Samsung SoC sound drivers from
broonie/sound because the cleanups there were part of this series and
all further patches depend on them.
* tag 'samsung-soc-s3c-5.10' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (62 commits)
ARM: s3c: Avoid naming clash of S3C24xx and S3C64xx timer setup
ARM: s3c: Cleanup from old plat-samsung include
ARM: s3c: make headers local if possible
ARM: s3c: move into a common directory
ARM: s3c24xx: stop including mach/hardware.h from mach/io.h
cpufreq: s3c24xx: move low-level clk reg access into platform code
cpufreq: s3c2412: use global s3c2412_cpufreq_setrefresh
ARM: s3c: remove cpufreq header dependencies
cpufreq: s3c24xx: split out registers
fbdev: s3c2410fb: remove mach header dependency
ARM: s3c24xx: bast: avoid irq_desc array usage
ARM: s3c24xx: spi: avoid hardcoding fiq number in driver
ARM: s3c24xx: include mach/irqs.h where needed
ARM: s3c24xx: move s3cmci pinctrl handling into board files
ARM: s3c24xx: move iis pinctrl config into boards
ARM: s3c24xx: move spi fiq handler into platform
ARM: s3c: adc: move header to linux/soc/samsung
ARM: s3c24xx: move irqchip driver back into platform
ARM: s3c24xx: move regs-spi.h into spi driver
ARM: s3c64xx: remove mach/hardware.h
...
Link: https://lore.kernel.org/r/20200831154751.7551-1-krzk@kernel.org
Signed-off-by: Olof Johansson <olof@lixom.net>
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Rather than have the cpufreq drivers touch include the
common headers to get the constants, add a small indirection.
This is still not the proper way that would do this through
the common clk API, but it lets us kill off the header file
usage.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Link: https://lore.kernel.org/r/20200806182059.2431-37-krzk@kernel.org
[krzk: Rebase and fix -Wold-style-definition]
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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There are two identical copies of the s3c2412_cpufreq_setrefresh
function: a static one in the cpufreq driver and a global
version in iotiming-s3c2412.c.
As the function requires the use of a hardcoded register address
from a header that we want to not be visible to drivers, just
move the existing global function and add a declaration in
one of the cpufreq header files.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Link: https://lore.kernel.org/r/20200806182059.2431-36-krzk@kernel.org
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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The cpufreq drivers are split between the machine directory
and the drivers/cpufreq directory. In order to share header
files after we convert s3c to multiplatform, those headers
have to live in a different global location.
Move them to linux/soc/samsung/ in lack of a better place.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Link: https://lore.kernel.org/r/20200806182059.2431-35-krzk@kernel.org
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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The s3c2410fb driver is too deeply intertwined with the s3c24xx
platform code. Change it in a way that avoids the use of platform
header files but having all interface data in a platform_data
header, and the private register definitions next to the driver
itself.
One ugly bit here is that the driver pokes directly into gpio
registers, which are owned by another driver. Passing the
mapped addresses in platform_data is somewhat suboptimal, but
it is a small improvement over the previous version.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20200806182059.2431-33-krzk@kernel.org
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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The IRQ_EINT0 constant is a platform detail that is
defined in mach/irqs.h and not visible to drivers once
that header is made private.
Since the same calculation already happens in s3c24xx_set_fiq,
just return the value from there.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20200806182059.2431-31-krzk@kernel.org
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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Rather than call the internal s3c_gpio_cfgall_range() function
through a platform header, move the code into the set_power
callback that is already exported by the board, and add
a default implementation.
In DT mode, the code already does not set the pin config,
so nothing changes there.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Link: https://lore.kernel.org/r/20200806182059.2431-29-krzk@kernel.org
[krzk: Rebase and correct set_power in mach-h1940.c]
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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The fiq handler needs access to some register definitions that
should not be used directly by device drivers.
Since this is closely related to the irqchip driver anyway,
move it into the same place.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
[krzk: Add a header guard in include/linux/spi/s3c24xx-fiq.h, fix
SPDX comment style, update maintainer's entry]
Co-developed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20200806182059.2431-23-krzk%40kernel.org
Acked-by: Mark Brown <broonie@kernel.org>
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There are multiple drivers using the private adc interface.
It seems unlikely that they would ever get converted to iio,
so make the current state official by making the header file
global.
The s3c2410_ts driver needs a couple of register definitions
as well.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Acked-by: Sebastian Reichel <sre@kernel.org>
Link: https://lore.kernel.org/r/20200806182059.2431-22-krzk@kernel.org
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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This is the only part of plat-samsung that is really
shared between the s3c and s5p ports. Moving it to
drivers/soc/ lets us make them completely independent.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20200806182059.2431-16-krzk@kernel.org
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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There is no real phy driver, so s3c-hsudc just pokes the registers
itself. Improve this a little by making it a platform data callback
like we do for gpios.
There is only one board using this driver, and it's unlikely
that another would be added, so this is a minimal workaround.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20200806182059.2431-9-krzk@kernel.org
[krzk: Include regs-s3c2443-clock.h in ifdef to fixup build on s3c6400]
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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Passing pointers directly as platform data is fragile and undocumented.
Better to create a platform data structure which explicitly documents
what is passed to the driver.
Suggested-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20200806182059.2431-6-krzk@kernel.org
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The s3c-camif driver setup platform code does not have any users so it
can be safely removed.
Along with the code W=1 compile warnings go away:
arch/arm/mach-s3c24xx/setup-camif.c:28:5: warning: no previous prototype for 's3c_camif_gpio_get' [-Wmissing-prototypes]
arch/arm/mach-s3c24xx/setup-camif.c:56:6: warning: no previous prototype for 's3c_camif_gpio_put' [-Wmissing-prototypes]
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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The s3c2410_common_clk_init() and others are defined and used by the
clk-s3c24xx driver and also used in the mach-s3c24xx machine code. Move
the declaration to a header to fix W=1 build warnings:
drivers/clk/samsung/clk-s3c2410.c:320:13: warning: no previous prototype for 's3c2410_common_clk_init' [-Wmissing-prototypes]
320 | void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
drivers/clk/samsung/clk-s3c2412.c:205:13: warning: no previous prototype for 's3c2412_common_clk_init' [-Wmissing-prototypes]
205 | void __init s3c2412_common_clk_init(struct device_node *np, unsigned long xti_f,
drivers/clk/samsung/clk-s3c2443.c:341:13: warning: no previous prototype for 's3c2443_common_clk_init' [-Wmissing-prototypes]
341 | void __init s3c2443_common_clk_init(struct device_node *np, unsigned long xti_f,
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
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The s3c64xx_clk_init() is defined and used by the clk-s3c64xx driver and
also used in the mach-s3c64xx machine code. Move the declaration to a
header to fix W=1 build warning:
drivers/clk/samsung/clk-s3c64xx.c:391:13: warning: no previous prototype for 's3c64xx_clk_init' [-Wmissing-prototypes]
391 | void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Tomasz Figa <tomasz.figa@gmail.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC fixes from Olof Johansson:
"I had queued up a batch of fixes that got a bit close to the release
for sending in before the merge window opened, so I'm including them
in the merge window batch instead.
Mostly smaller DT tweaks and fixes, the usual mix that we tend to have
through the releases"
* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
ARM: dts: iwg20d-q7-common: Fix touch controller probe failure
ARM: OMAP2+: Restore MPU power domain if cpu_cluster_pm_enter() fails
ARM: dts: am33xx: modify AM33XX_IOPAD for #pinctrl-cells = 2
soc: actions: include header to fix missing prototype
arm64: dts: ti: k3-j721e: Rename mux header and update macro names
soc: qcom: pdr: Fixup array type of get_domain_list_resp message
arm64: dts: qcom: pm660: Fix missing pound sign in interrupt-cells
arm64: dts: qcom: kitakami: Temporarily disable SDHCI1
arm64: dts: sdm630: Temporarily disable SMMUs by default
arm64: dts: sdm845: Fixup OPP table for all qup devices
arm64: dts: allwinner: h5: remove Mali GPU PMU module
ARM: dts: sun8i: r40: bananapi-m2-ultra: Fix dcdc1 regulator
soc: xilinx: Fix error code in zynqmp_pm_probe()
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git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/fixes
Two regression fixes for omaps
Fix AM33XX_IOPAD macro that broke after recent pinctrl changes
to use #pinctrl-cells = 2. And fix omap_enter_idle_coupled()
for cases where cpu_cluster_pm_enter() returns an error as
otherwise we may end up wrongly idling the MPU domain on the
next WFI.
* tag 'omap-for-v5.9/fixes-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: Restore MPU power domain if cpu_cluster_pm_enter() fails
ARM: dts: am33xx: modify AM33XX_IOPAD for #pinctrl-cells = 2
Link: https://lore.kernel.org/r/pull-1601544624-617679@atomide.com
Signed-off-by: Olof Johansson <olof@lixom.net>
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