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* selftests/powerpc: Fix incorrect kernel headers search pathMathieu Desnoyers2023-02-154-4/+4
| | | | | | | | | | | | | Use $(KHDR_INCLUDES) as lookup path for kernel headers. This prevents building against kernel headers from the build environment in scenarios where kernel headers are installed into a specific output directory (O=...). Cc: stable@vger.kernel.org # v5.18+ Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> Acked-by: Shuah Khan <skhan@linuxfoundation.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20230127135755.79929-22-mathieu.desnoyers@efficios.com
* selftests/powerpc: Add automatically allocating read_fileBenjamin Gray2023-02-095-109/+71
| | | | | | | | | | | A couple of tests roll their own auto-allocating file read logic. Add a generic implementation and convert them to use it. Signed-off-by: Benjamin Gray <bgray@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20230203003947.38033-6-bgray@linux.ibm.com
* selftests/powerpc: Add {read,write}_{long,ulong}Benjamin Gray2023-02-095-22/+95
| | | | | | | | | | | Add helper functions to read and write (unsigned) long values directly from/to files. One of the kernel interfaces uses hex strings, so we need to allow passing a base too. Signed-off-by: Benjamin Gray <bgray@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20230203003947.38033-5-bgray@linux.ibm.com
* selftests/powerpc: Parse long/unsigned long value safelyBenjamin Gray2023-02-093-7/+132
| | | | | | | | | | | | | | Often a file is expected to hold an integral value. Existing functions will use a C stdlib function like atoi or strtol to parse the file. These operations are error prone, with complicated error conditions (atoi returns 0 if not a number, and is undefined behaviour if not in range. strtol returns 0 if not a number, and LONG_MIN/MAX if not in range + sets errno to ERANGE). Signed-off-by: Benjamin Gray <bgray@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20230203003947.38033-4-bgray@linux.ibm.com
* selftests/powerpc: Add read/write debugfs file, intBenjamin Gray2023-02-095-35/+47
| | | | | | | | | | | | Debugfs files are not always integers, so make *_file return/write a byte buffer, and *_int deal with int values specifically. This increases consistency with the other file read/write helpers. Signed-off-by: Benjamin Gray <bgray@linux.ibm.com> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20230203003947.38033-3-bgray@linux.ibm.com
* selftests/powerpc: Add generic read/write file utilBenjamin Gray2023-02-097-160/+120
| | | | | | | | | | | | | File read/write is reimplemented in about 5 different ways in the various PowerPC selftests. This indicates it should be a common util. Add a common read_file / write_file implementation and convert users to it where (easily) possible. Signed-off-by: Benjamin Gray <bgray@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20230203003947.38033-2-bgray@linux.ibm.com
* selftests/powerpc: Fix resource leaksMiaoqian Lin2022-12-051-1/+4
| | | | | | | | | | | | | | In check_all_cpu_dscr_defaults, opendir() opens the directory stream. Add missing closedir() in the error path to release it. In check_cpu_dscr_default, open() creates an open file descriptor. Add missing close() in the error path to release it. Fixes: ebd5858c904b ("selftests/powerpc: Add test for all DSCR sysfs interfaces") Signed-off-by: Miaoqian Lin <linmq006@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20221205084429.570654-1-linmq006@gmail.com
* selftests/powerpc: Add ptrace setup_core_pattern() null-terminatorBenjamin Gray2022-12-021-1/+3
| | | | | | | | | | | | | | | - malloc() does not zero the buffer, - fread() does not null-terminate it's output, - `cat /proc/sys/kernel/core_pattern | hexdump -C` shows the file is not inherently null-terminated So using string operations on the buffer is risky. Explicitly add a null character to the end to make it safer. Signed-off-by: Benjamin Gray <bgray@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20221128041948.58339-3-bgray@linux.ibm.com
* selftests/powerpc: Use mfspr/mtspr macrosBenjamin Gray2022-12-024-21/+10
| | | | | | | | | | | No need to write inline asm for mtspr/mfspr, we have macros for this in reg.h Signed-off-by: Benjamin Gray <bgray@linux.ibm.com> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20221128041948.58339-2-bgray@linux.ibm.com
* selftests: powerpc: Use "grep -E" instead of "egrep"Tiezhu Yang2022-12-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | The latest version of grep claims the egrep is now obsolete so the build now contains warnings that look like: egrep: warning: egrep is obsolescent; using grep -E fix this using "grep -E" instead. sed -i "s/egrep/grep -E/g" `grep egrep -rwl tools/testing/selftests/powerpc` Here are the steps to install the latest grep: wget http://ftp.gnu.org/gnu/grep/grep-3.8.tar.gz tar xf grep-3.8.tar.gz cd grep-3.8 && ./configure && make sudo make install export PATH=/usr/local/bin:$PATH Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/1669862997-31335-1-git-send-email-yangtiezhu@loongson.cn
* selftests/powerpc: Account for offline cpus in perf-hwbreak testNaveen N. Rao2022-11-301-6/+39
| | | | | | | | | | For systemwide tests, use online cpu mask to only open events on online cpus. This enables this test to work on systems in lower SMT modes. Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/15fd447dcefd19945a7d31f0a475349f548a3603.1669096083.git.naveen.n.rao@linux.vnet.ibm.com
* selftests/powerpc: Bump up rlimit for perf-hwbreak testNaveen N. Rao2022-11-301-0/+12
| | | | | | | | | | | | | The systemwide perf hardware breakpoint test tries to open a perf event on each cpu. On large systems, we run out of file descriptors and fail the test. Instead, have the test set the file descriptor limit to an arbitraty high value. Reported-by: Rohan Deshpande <rohan_d@linux.vnet.ibm.com> Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/187fed5843cecc1e5066677b6296ee88337d7bef.1669096083.git.naveen.n.rao@linux.vnet.ibm.com
* selftests/powerpc: Move perror closer to its useNaveen N. Rao2022-11-301-16/+5
| | | | | | | | | | | Right now, if perf_event_open() fails for the systemwide tests, error report is printed too late, sometimes after subsequent system calls. Move use of perror() to the main function, just after the syscall. Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/372ac78c27899f1f612fbd6ac796604a4a9310aa.1669096083.git.naveen.n.rao@linux.vnet.ibm.com
* selftests/powerpc: Remove repeated word in commentsShaomin Deng2022-11-241-1/+1
| | | | | | | | | Remove the repeated word "not" in comments. Signed-off-by: Shaomin Deng <dengshaomin@cdjrlc.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20221029094643.5595-1-dengshaomin@cdjrlc.com
* selftests/powerpc: Fix spelling mistake "mmaping" -> "mmapping"Colin Ian King2022-11-241-1/+1
| | | | | | | | | There is a spelling mistake in a perror message. Fix it. Signed-off-by: Colin Ian King <colin.i.king@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20221021084545.65973-1-colin.i.king@gmail.com
* selftests/powerpc: Update bhrb filter sampling test for multiple branch filtersAthira Rajeev2022-09-281-0/+9
| | | | | | | | | | | | | | | | For PERF_SAMPLE_BRANCH_STACK sample type, different branch_sample_type, ie branch filters are supported. The testcase "bhrb_filter_map_test" tests the valid and invalid filter maps in different powerpc platforms. Update this testcase to include scenario to cover multiple branch filters at sametime. Since powerpc doesn't support multiple filters at sametime, expect failure during perf_event_open. Reported-by: Disha Goel <disgoel@linux.vnet.ibm.com> Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com> Reviewed-by: Kajol Jain <kjain@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220921145255.20972-3-atrajeev@linux.vnet.ibm.com
* selftests/powerpc: Skip 4PB test on 4K PAGE_SIZE systemsMichael Ellerman2022-09-041-0/+2
| | | | | | | | | Systems using the hash MMU with a 4K page size don't support 4PB address space, so skip the test because the bug it tests for can't be triggered. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220901020215.254097-1-mpe@ellerman.id.au
* selftests/powerpc: Add a test for execute-only memoryNicholas Miehlbradt2022-08-262-1/+233
| | | | | | | | | | | | | | This selftest is designed to cover execute-only protections on the Radix MMU but will also work with Hash. The tests are based on those found in pkey_exec_test with modifications to use the generic mprotect() instead of the pkey variants. Signed-off-by: Nicholas Miehlbradt <nicholas@linux.ibm.com> Signed-off-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220817050640.406017-2-ruscur@russell.cc
* powerpc/selftests: Use timersub() for gettimeofday()ye xingchen2022-08-221-2/+4
| | | | | | | | | | Use timersub() function to simplify the code. Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220816105106.82666-1-ye.xingchen@zte.com.cn
* selftests/powerpc: Add missing PMU selftests to .gitignoresRussell Currey2022-08-152-4/+34
| | | | | | | | | | | | | Some recently added selftests don't have their binaries in .gitignores, so add them. I also alphabetically sorted sampling_tests/.gitignore while I was in there. Signed-off-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220812071632.56095-1-ruscur@russell.cc
* selftests/powerpc: Avoid GCC 12 uninitialised variable warningMichael Ellerman2022-08-011-0/+1
| | | | | | | | | | | | | | | | GCC 12 thinks that `actual` might be used uninitialised. It's not, the use is guarded by `bad_mmcr2` which is only set to true at the same point where `actual` is initialised. cycles_with_mmcr2_test.c: In function ‘cycles_with_mmcr2’: cycles_with_mmcr2_test.c:81:17: error: ‘actual’ may be used uninitialized [-Werror=maybe-uninitialized] 81 | printf("Bad MMCR2 value seen is 0x%lx\n", actual); Silence the warning by initialising `actual` to zero. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220801113746.802046-1-mpe@ellerman.id.au
* selftests/powerpc: Fix matrix multiply assist testRashmica Gupta2022-07-281-0/+3
| | | | | | | | | | | | | | | | | | The ISA states: "when ACC[i] contains defined data, the contents of VSRs 4×i to 4×i+3 are undefined until either a VSX Move From ACC instruction is used to copy the contents of ACC[i] to VSRs 4×i to 4×i+3 or some other instruction directly writes to one of these VSRs." We aren't doing this. This test only works on Power10 because the hardware implementation happens to map ACC0 to VSRs 0-3, but will fail on any other implementation that doesn't do this. So add xxmfacc between writing to the accumulator and accessing the VSRs. Fixes: 3527e1ab9a79 ("selftests/powerpc: Add matrix multiply assist (MMA) test") Signed-off-by: Rashmica Gupta <rashmica@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220617043935.428083-1-rashmica@linux.ibm.com
* selftests/powerpc/ptrace: Add peek/poke of FPRsMichael Ellerman2022-07-252-2/+87
| | | | | | | | | | | | | | Currently the ptrace-gpr test only tests the GET/SET(FP)REGS ptrace APIs. But there's an alternate (older) API, called PEEK/POKEUSR. Add some minimal testing of PEEK/POKEUSR of the FPRs. This is sufficient to detect the bug that was fixed recently in the 32-bit ptrace FPR handling. Depends-on: 8e1278444446 ("powerpc/32: Fix overread/overwrite of thread_struct via ptrace") Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220627140239.2464900-13-mpe@ellerman.id.au
* selftests/powerpc/ptrace: Use more interesting valuesMichael Ellerman2022-07-251-14/+57
| | | | | | | | | | | | | The ptrace-gpr test uses fixed values to test that registers can be read/written via ptrace. In particular it sets all GPRs to 1, which means the test could miss some types of bugs - eg. if the kernel was only returning the low word. So generate some random values at startup and use those instead. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220627140239.2464900-12-mpe@ellerman.id.au
* selftests/powerpc/ptrace: Make child errors more obviousMichael Ellerman2022-07-251-8/+5
| | | | | | | | | Use the FAIL_IF() macro so that errors in the child report a line number, rather than just silently exiting. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220627140239.2464900-11-mpe@ellerman.id.au
* selftests/powerpc/ptrace: Do more of ptrace-gpr in asmMichael Ellerman2022-07-254-17/+73
| | | | | | | | | | | | | | | | | | The ptrace-gpr test includes some inline asm to load GPR and FPR registers. It then goes back to C to wait for the parent to trace it and then checks register contents. The split between inline asm and C is fragile, it relies on the compiler not using any non-volatile GPRs after the inline asm block. It also requires a very large and unwieldy inline asm block. So convert the logic to set registers, wait, and store registers to a single asm function, meaning there's no window for the compiler to intervene. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220627140239.2464900-10-mpe@ellerman.id.au
* selftests/powerpc/ptrace: Build the ptrace-gpr test as 32-bit when possibleMichael Ellerman2022-07-251-2/+3
| | | | | | | | | The ptrace-gpr test can now be built 32-bit, so do that if that's the compiler default rather than forcing a 64-bit build. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220627140239.2464900-9-mpe@ellerman.id.au
* selftests/powerpc/ptrace: Convert to load/store doublesMichael Ellerman2022-07-257-109/+111
| | | | | | | | | | | Some of the ptrace tests check the contents of floating pointer registers. Currently these use float, which is always 4 bytes, but the ptrace API supports saving/restoring 8 bytes per register, so switch to using doubles to exercise the code more fully. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220627140239.2464900-8-mpe@ellerman.id.au
* selftests/powerpc/ptrace: Drop unused load_fpr_single_precision()Michael Ellerman2022-07-252-38/+0
| | | | | | | | This function is never called, drop it. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220627140239.2464900-7-mpe@ellerman.id.au
* selftests/powerpc: Add 32-bit support to asm helpersMichael Ellerman2022-07-251-9/+38
| | | | | | | | Add support for 32-bit builds to the asm helpers. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220627140239.2464900-6-mpe@ellerman.id.au
* selftests/powerpc: Don't save TOC by default in asm helpersMichael Ellerman2022-07-251-3/+1
| | | | | | | | | | Thare are some asm helpers for creating/popping stack frames in basic_asm.h. They always save/restore r2 (TOC pointer), but none of the selftests change r2, so it's unnecessary to save it by default. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220627140239.2464900-5-mpe@ellerman.id.au
* selftests/powerpc: Don't save CR by default in asm helpersMichael Ellerman2022-07-251-4/+0
| | | | | | | | | | | Thare are some asm helpers for creating/popping stack frames in basic_asm.h. They always save/restore CR, but none of the selftests tests touch non-volatile CR fields, so it's unnecessary to save them by default. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220627140239.2464900-4-mpe@ellerman.id.au
* selftests/powerpc/ptrace: Split CFLAGS betterMichael Ellerman2022-07-251-5/+28
| | | | | | | | | | | | | | | Currently all ptrace tests are built 64-bit and with TM enabled. Only the TM tests need TM enabled, so split those out into a separate variable so that can be specified precisely. Split the rest of the tests into a variable, and add -m64 to CFLAGS for those tests, so that in a subsequent patch some tests can be made to build 32-bit. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220627140239.2464900-3-mpe@ellerman.id.au
* selftests/powerpc/ptrace: Set LOCAL_HDRSMichael Ellerman2022-07-251-2/+3
| | | | | | | | | | Set LOCAL_HDRS so header changes cause rebuilds. The lib.mk logic adds all the headers in LOCAL_HDRS as dependencies, so there's no need to also list them explicitly. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220627140239.2464900-2-mpe@ellerman.id.au
* selftests/powerpc: Ensure 16-byte stack pointer alignmentMichael Ellerman2022-07-251-2/+2
| | | | | | | | | | | | | | | The PUSH/POP_BASIC_STACK helpers in basic_asm.h do not ensure that the stack pointer is always 16-byte aligned, which is required per the ABI. Fix the macros to do the alignment if the caller fails to. Currently only one caller passes a non-aligned size, tm_signal_self(), which hasn't been caught in testing, presumably because it's a leaf function. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220627140239.2464900-1-mpe@ellerman.id.au
* selftests/powerpc: Add missing files to .gitignoresMichael Ellerman2022-06-294-0/+4
| | | | | | | These were missed when the respective tests were added, add them now. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220616070705.1941829-1-mpe@ellerman.id.au
* selftests/powerpc/pmu: Add test for hardware cache eventsKajol Jain2022-06-292-1/+90
| | | | | | | | | | | | | | | | The testcase checks if the transalation of a generic hardware cache event is done properly via perf interface. The hardware cache events has type as PERF_TYPE_HW_CACHE and each event points to raw event code id. Testcase checks different combination of cache level, cache event operation type and cache event result type and verify for a given event code, whether transalation matches with the current cache event mappings via perf interface. Signed-off-by: Kajol Jain <kjain@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220610134113.62991-36-atrajeev@linux.vnet.ibm.com
* selftests/powerpc/pmu: Add selftest for group constraint check for MMCRA ↵Kajol Jain2022-06-292-1/+64
| | | | | | | | | | | | | | | | | | | thresh_sel field Thresh select bits in the event code is used to program thresh_sel field in Monitor Mode Control Register A (MMCRA: 45-47). When scheduling events as a group, all events in that group should match value in these bits. Otherwise event open for the sibling events will fail. Testcase uses event code PM_MRK_INST_CMPL (0x401e0) as leader and another event PM_THRESH_MET (0x101ec) as sibling event, and checks if group constraint checks for thresh_sel field added correctly via perf interface. Signed-off-by: Kajol Jain <kjain@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220610134113.62991-35-atrajeev@linux.vnet.ibm.com
* selftests/powerpc/pmu: Add selftest for group constraint check for MMCRA ↵Kajol Jain2022-06-292-1/+65
| | | | | | | | | | | | | | | | | | | thresh_ctl field Thresh control bits in the event code is used to program thresh_ctl field in Monitor Mode Control Register A (MMCRA: 48-55). When scheduling events as a group, all events in that group should match value in these bits. Otherwise event open for the sibling events will fail. Testcase uses event code PM_MRK_INST_CMPL (0x401e0) as leader and another event PM_THRESH_MET (101ec) as sibling event, and checks if group constraint checks for thresh_ctl field added correctly via perf interface. Signed-off-by: Kajol Jain <kjain@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220610134113.62991-34-atrajeev@linux.vnet.ibm.com
* selftests/powerpc/pmu: Add selftest for group constraint for unit and pmc ↵Kajol Jain2022-06-292-1/+76
| | | | | | | | | | | | | | field in p9 Unit and pmu bits in the event code is used to program unit and pmc fields in Monitor Mode Control Register 1 (MMCR1). For power9 platform, incase unit field value is within 6 to 9, one of the event in the group should use PMC4. Otherwise event_open should fail for that group. Signed-off-by: Kajol Jain <kjain@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220610134113.62991-33-atrajeev@linux.vnet.ibm.com
* selftests/powerpc/pmu: Add selftest for group constraint check for MMCRA ↵Kajol Jain2022-06-292-1/+97
| | | | | | | | | | | | | | | | | | | thresh_cmp field Thresh compare bits for a event is used to program thresh compare field in Monitor Mode Control Register A (MMCRA: 9-18 bits for power9 and MMCRA: 8-18 bits for power10). When scheduling events as a group, all events in that group should match value in thresh compare bits. Otherwise event open for the sibling events will fail. Testcase uses event code "0x401e0" as leader and another event "0x101ec" as sibling event, and checks for thresh compare constraint via perf interface. Signed-off-by: Kajol Jain <kjain@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220610134113.62991-32-atrajeev@linux.vnet.ibm.com
* selftests/powerpc/pmu: Add selftest for group constraint check for MMCR1 ↵Kajol Jain2022-06-292-1/+61
| | | | | | | | | | | | | | | | | | | cache bits Data and instruction cache qualifier bits in the event code is used to program cache select field in Monitor Mode Control Register 1 (MMCR1: 16-17). When scheduling events as a group, all events in that group should match value in these bits. Otherwise event open for the sibling events will fail. Testcase uses event code "0x1100fc" as leader and other events like "0x23e054" and "0x13e054" as sibling events to checks for l1 cache select field constraints via perf interface. Signed-off-by: Kajol Jain <kjain@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220610134113.62991-31-atrajeev@linux.vnet.ibm.com
* selftests/powerpc/pmu: Add selftest for group constraint check for MMCR0 ↵Kajol Jain2022-06-292-1/+66
| | | | | | | | | | | | | | | | | | | l2l3_sel bits In power10, L2L3 select bits in the event code is used to program l2l3_sel field in Monitor Mode Control Register 0 (MMCR0: 56-60). When scheduling events as a group, all events in that group should match value in these bits. Otherwise event open for the sibling events will fail. Testcase uses event code "0x010000046080" as leader and another events "0x26880" and "0x010000026880" as sibling events, and checks for l2l3_sel constraints via perf interface for ISA v3.1 platform. Signed-off-by: Kajol Jain <kjain@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220610134113.62991-30-atrajeev@linux.vnet.ibm.com
* selftests/powerpc/pmu: Add selftest for PERF_TYPE_HARDWARE events valid checkAthira Rajeev2022-06-292-1/+131
| | | | | | | | | | | | | | | | | | | | | Testcase to ensure that using invalid event in generic event for PERF_TYPE_HARDWARE will fail. Invalid generic events in power10 are: - PERF_COUNT_HW_BUS_CYCLES - PERF_COUNT_HW_STALLED_CYCLES_FRONTEND - PERF_COUNT_HW_STALLED_CYCLES_BACKEND - PERF_COUNT_HW_REF_CPU_CYCLES Invalid generic events in power9 are: - PERF_COUNT_HW_BUS_CYCLES - PERF_COUNT_HW_REF_CPU_CYCLES Testcase does event open for valid and invalid generic events to ensure event open works for all valid events and fails for invalid events. Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220610134113.62991-29-atrajeev@linux.vnet.ibm.com
* selftests/powerpc/pmu: Add selftest for event alternatives for power10Athira Rajeev2022-06-292-1/+110
| | | | | | | | | | | | | | | | | | | | Platform specific PMU supports alternative event for some of the event codes. During perf_event_open, it any event group doesn't match constraint check criteria, further lookup is done to find alternative event. Code checks to see if it is possible to schedule event as group using alternative events. Testcase exercises the alternative event find code for power10. Example, Using PMC1 to PMC4 in a group and again trying to schedule PM_CYC_ALT (0x0001e) will fail since this exceeds number of programmable events in group. But since 0x600f4 is an alternative event for 0x0001e, it is possible to use 0x0001e in the group. Testcase uses such combination all events in power10 which has alternative event. Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220610134113.62991-28-atrajeev@linux.vnet.ibm.com
* selftests/powerpc/pmu: Add selftest for event alternatives for power9Athira Rajeev2022-06-292-1/+117
| | | | | | | | | | | | | | | | | | | | Platform specific PMU supports alternative event for some of the event codes. During perf_event_open, it any event group doesn't match constraint check criteria, further lookup is done to find alternative event. Code checks to see if it is possible to schedule event as group using alternative events. Testcase exercises the alternative event find code for power9. Example, since events in same PMC can't go in as a group, ideally using PM_RUN_CYC_ALT (0x200f4) and PM_BR_TAKEN_CMPL (0x200fa) will fail. But since RUN_CYC (0x600f4) is alternative event for 0x200f4, it is possible to use 0x600f4 and 0x200fa as group. Testcase uses such combination for all events in power9 which has an alternative event. Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220610134113.62991-27-atrajeev@linux.vnet.ibm.com
* selftests/powerpc/pmu: Add selftest for blacklist events check in power9Athira Rajeev2022-06-292-1/+134
| | | | | | | | | | | | | | Some of the events are blacklisted in power9. The list of blacklisted events are noted in power9-events-list.h When trying to do event open for any of these blacklisted event will cause a failure. Testcase ensures that using blacklisted events will cause event_open to fail in power9. This test is only applicable on power9 DD2.1 and DD2.2 and hence test adds checks to skip on other platforms. Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220610134113.62991-26-atrajeev@linux.vnet.ibm.com
* selftests/powerpc/pmu: Add selftest for reserved bit check for MMCRA ↵Athira Rajeev2022-06-292-1/+45
| | | | | | | | | | | | | thresh_ctl field Testcase for reserved bits in Monitor Mode Control Register A (MMCRA) thresh_ctl bits. For MMCRA[48:51]/[52:55]) Threshold Start/Stop, 0b11110000/0b00001111 is reserved. Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220610134113.62991-25-atrajeev@linux.vnet.ibm.com
* selftests/powerpc/pmu: Add selftest for checking invalid bits in event codeAthira Rajeev2022-06-292-1/+68
| | | | | | | | | | | | | | | | Some of the bits in the event code is reserved for specific platforms. Event code bits 52-59 are reserved in power9, whereas in power10, these are used for programming Monitor Mode Control Register 3 (MMCR3). Bit 9 in event code is reserved in power9, whereas it is used for programming "radix_scope_qual" bit 18 in Monitor Mode Control Register 1 (MMCR1). Testcase to ensure that using reserved bits in event code should cause event_open to fail. Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220610134113.62991-24-atrajeev@linux.vnet.ibm.com
* selftests/powerpc/pmu: Add selftest for group constraint check MMCRA sample bitsAthira Rajeev2022-06-292-1/+56
| | | | | | | | | | | | | | Events with different "sample" field values which is used to program Monitor Mode Control Register A (MMCRA) in a group will fail to schedule. Testcase uses event with load only sampling mode as group leader and event with store only sampling as sibling event. So that it can check that using different sample bits in event code will fail in event open for group of events Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220610134113.62991-23-atrajeev@linux.vnet.ibm.com
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