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HiSilicon STB PCIe host bridge DT description
The HiSilicon STB PCIe host controller is based on the DesignWare PCIe core.
It shares common functions with the DesignWare PCIe core driver and inherits
common properties defined in
Documentation/devicetree/bindings/pci/designware-pcie.txt.
Additional properties are described here:
Required properties
- compatible: Should be one of the following strings:
"hisilicon,hi3798cv200-pcie"
- reg: Should contain sysctl, rc_dbi, config registers location and length.
- reg-names: Must include the following entries:
"control": control registers of PCIe controller;
"rc-dbi": configuration space of PCIe controller;
"config": configuration transaction space of PCIe controller.
- bus-range: PCI bus numbers covered.
- interrupts: MSI interrupt.
- interrupt-names: Must include "msi" entries.
- clocks: List of phandle and clock specifier pairs as listed in clock-names
property.
- clock-name: Must include the following entries:
"aux": auxiliary gate clock;
"pipe": pipe gate clock;
"sys": sys gate clock;
"bus": bus gate clock.
- resets: List of phandle and reset specifier pairs as listed in reset-names
property.
- reset-names: Must include the following entries:
"soft": soft reset;
"sys": sys reset;
"bus": bus reset.
Optional properties:
- reset-gpios: The gpio to generate PCIe PERST# assert and deassert signal.
- phys: List of phandle and phy mode specifier, should be 0.
- phy-names: Must be "phy".
Example:
pcie@f9860000 {
compatible = "hisilicon,hi3798cv200-pcie";
reg = <0xf9860000 0x1000>,
<0xf0000000 0x2000>,
<0xf2000000 0x01000000>;
reg-names = "control", "rc-dbi", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0 15>;
num-lanes = <1>;
ranges=<0x81000000 0 0 0xf4000000 0 0x00010000
0x82000000 0 0xf3000000 0xf3000000 0 0x01000000>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg PCIE_AUX_CLK>,
<&crg PCIE_PIPE_CLK>,
<&crg PCIE_SYS_CLK>,
<&crg PCIE_BUS_CLK>;
clock-names = "aux", "pipe", "sys", "bus";
resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>;
reset-names = "soft", "sys", "bus";
phys = <&combphy1 PHY_TYPE_PCIE>;
phy-names = "phy";
};
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