summaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts/imx53-mba53.dts
blob: e54fffd483690300c2a89e6719a2621b03aa75bb (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
/*
 * Copyright 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
 * Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>, Pengutronix
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

/dts-v1/;
/include/ "imx53-tqma53.dtsi"

/ {
	model = "TQ MBa53 starter kit";
	compatible = "tq,mba53", "tq,tqma53", "fsl,imx53";
};

&iomuxc {
	lvds1 {
		pinctrl_lvds1_1: lvds1-grp1 {
			fsl,pins = <730 0x10000		/* LVDS0_TX3 */
				    732 0x10000		/* LVDS0_CLK */
				    734 0x10000		/* LVDS0_TX2 */
				    736 0x10000		/* LVDS0_TX1 */
				    738 0x10000>;	/* LVDS0_TX0 */
		};

		pinctrl_lvds1_2: lvds1-grp2 {
			fsl,pins = <720 0x10000		/* LVDS1_TX3 */
				    722 0x10000		/* LVDS1_TX2 */
				    724 0x10000		/* LVDS1_CLK */
				    726 0x10000		/* LVDS1_TX1 */
				    728 0x10000>;	/* LVDS1_TX0 */
		};
	};

	disp1 {
		pinctrl_disp1_1: disp1-grp1 {
			fsl,pins = <689 0x10000		/* DISP1_DRDY	*/
				    482 0x10000		/* DISP1_HSYNC	*/
				    489 0x10000		/* DISP1_VSYNC	*/
				    684 0x10000		/* DISP1_DAT_0	*/
				    515 0x10000		/* DISP1_DAT_22	*/
				    523 0x10000		/* DISP1_DAT_23	*/
				    543 0x10000		/* DISP1_DAT_21	*/
				    553 0x10000		/* DISP1_DAT_20	*/
				    558 0x10000		/* DISP1_DAT_19	*/
				    564 0x10000		/* DISP1_DAT_18	*/
				    570 0x10000		/* DISP1_DAT_17	*/
				    575 0x10000		/* DISP1_DAT_16	*/
				    580 0x10000		/* DISP1_DAT_15	*/
				    585 0x10000		/* DISP1_DAT_14	*/
				    590 0x10000		/* DISP1_DAT_13	*/
				    595 0x10000		/* DISP1_DAT_12	*/
				    628 0x10000		/* DISP1_DAT_11	*/
				    634 0x10000		/* DISP1_DAT_10	*/
				    639 0x10000		/* DISP1_DAT_9	*/
				    644 0x10000		/* DISP1_DAT_8	*/
				    649 0x10000		/* DISP1_DAT_7	*/
				    654 0x10000		/* DISP1_DAT_6	*/
				    659 0x10000		/* DISP1_DAT_5	*/
				    664 0x10000		/* DISP1_DAT_4	*/
				    669 0x10000		/* DISP1_DAT_3	*/
				    674 0x10000		/* DISP1_DAT_2	*/
				    679 0x10000		/* DISP1_DAT_1	*/
				    684 0x10000>;	/* DISP1_DAT_0	*/
		};
	};
};

&cspi {
	status = "okay";
};

&i2c2 {
	codec: sgtl5000@a {
		compatible = "fsl,sgtl5000";
		reg = <0x0a>;
	};

	expander: pca9554@20 {
		compatible = "pca9554";
		reg = <0x20>;
		interrupts = <109>;
	};

	sensor2: lm75@49 {
		compatible = "lm75";
		reg = <0x49>;
	};
};

&fec {
	status = "okay";
};

&esdhc2 {
	status = "okay";
};

&uart3 {
	status = "okay";
};

&ecspi1 {
	status = "okay";
};

&uart1 {
	status = "okay";
};

&uart2 {
	status = "okay";
};

&can1 {
	status = "okay";
};

&can2 {
	status = "okay";
};

&i2c3 {
	status = "okay";
};