summaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts/rk3066a.dtsi
blob: 653127a377faa5388f64e003e7b09c73d72286bc (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2013 MundoReader S.L.
 * Author: Heiko Stuebner <heiko@sntech.de>
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3066a-cru.h>
#include <dt-bindings/power/rk3066-power.h>
#include "rk3xxx.dtsi"

/ {
	compatible = "rockchip,rk3066a";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "rockchip,rk3066-smp";

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x0>;
			operating-points = <
				/* kHz    uV */
				1416000 1300000
				1200000 1175000
				1008000 1125000
				816000  1125000
				600000  1100000
				504000  1100000
				312000  1075000
			>;
			clock-latency = <40000>;
			clocks = <&cru ARMCLK>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x1>;
		};
	};

	display-subsystem {
		compatible = "rockchip,display-subsystem";
		ports = <&vop0_out>, <&vop1_out>;
	};

	sram: sram@10080000 {
		compatible = "mmio-sram";
		reg = <0x10080000 0x10000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x10080000 0x10000>;

		smp-sram@0 {
			compatible = "rockchip,rk3066-smp-sram";
			reg = <0x0 0x50>;
		};
	};

	vop0: vop@1010c000 {
		compatible = "rockchip,rk3066-vop";
		reg = <0x1010c000 0x19c>;
		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_LCDC0>,
			 <&cru DCLK_LCDC0>,
			 <&cru HCLK_LCDC0>;
		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
		power-domains = <&power RK3066_PD_VIO>;
		resets = <&cru SRST_LCDC0_AXI>,
			 <&cru SRST_LCDC0_AHB>,
			 <&cru SRST_LCDC0_DCLK>;
		reset-names = "axi", "ahb", "dclk";
		status = "disabled";

		vop0_out: port {
			#address-cells = <1>;
			#size-cells = <0>;
		};
	};

	vop1: vop@1010e000 {
		compatible = "rockchip,rk3066-vop";
		reg = <0x1010e000 0x19c>;
		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_LCDC1>,
			 <&cru DCLK_LCDC1>,
			 <&cru HCLK_LCDC1>;
		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
		power-domains = <&power RK3066_PD_VIO>;
		resets = <&cru SRST_LCDC1_AXI>,
			 <&cru SRST_LCDC1_AHB>,
			 <&cru SRST_LCDC1_DCLK>;
		reset-names = "axi", "ahb", "dclk";
		status = "disabled";

		vop1_out: port {
			#address-cells = <1>;
			#size-cells = <0>;
		};
	};

	i2s0: i2s@10118000 {
		compatible = "rockchip,rk3066-i2s";
		reg = <0x10118000 0x2000>;
		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2s0_bus>;
		dmas = <&dmac1_s 4>, <&dmac1_s 5>;
		dma-names = "tx", "rx";
		clock-names = "i2s_hclk", "i2s_clk";
		clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
		rockchip,playback-channels = <8>;
		rockchip,capture-channels = <2>;
		#sound-dai-cells = <0>;
		status = "disabled";
	};

	i2s1: i2s@1011a000 {
		compatible = "rockchip,rk3066-i2s";
		reg = <0x1011a000 0x2000>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2s1_bus>;
		dmas = <&dmac1_s 6>, <&dmac1_s 7>;
		dma-names = "tx", "rx";
		clock-names = "i2s_hclk", "i2s_clk";
		clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>;
		rockchip,playback-channels = <2>;
		rockchip,capture-channels = <2>;
		#sound-dai-cells = <0>;
		status = "disabled";
	};

	i2s2: i2s@1011c000 {
		compatible = "rockchip,rk3066-i2s";
		reg = <0x1011c000 0x2000>;
		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2s2_bus>;
		dmas = <&dmac1_s 9>, <&dmac1_s 10>;
		dma-names = "tx", "rx";
		clock-names = "i2s_hclk", "i2s_clk";
		clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>;
		rockchip,playback-channels = <2>;
		rockchip,capture-channels = <2>;
		#sound-dai-cells = <0>;
		status = "disabled";
	};

	cru: clock-controller@20000000 {
		compatible = "rockchip,rk3066a-cru";
		reg = <0x20000000 0x1000>;
		rockchip,grf = <&grf>;

		#clock-cells = <1>;
		#reset-cells = <1>;
		assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>,
				  <&cru ACLK_CPU>, <&cru HCLK_CPU>,
				  <&cru PCLK_CPU>, <&cru ACLK_PERI>,
				  <&cru HCLK_PERI>, <&cru PCLK_PERI>;
		assigned-clock-rates = <400000000>, <594000000>,
				       <300000000>, <150000000>,
				       <75000000>, <300000000>,
				       <150000000>, <75000000>;
	};

	timer@2000e000 {
		compatible = "snps,dw-apb-timer-osc";
		reg = <0x2000e000 0x100>;
		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
		clock-names = "timer", "pclk";
	};

	efuse: efuse@20010000 {
		compatible = "rockchip,rk3066a-efuse";
		reg = <0x20010000 0x4000>;
		#address-cells = <1>;
		#size-cells = <1>;
		clocks = <&cru PCLK_EFUSE>;
		clock-names = "pclk_efuse";

		cpu_leakage: cpu_leakage@17 {
			reg = <0x17 0x1>;
		};
	};

	timer@20038000 {
		compatible = "snps,dw-apb-timer-osc";
		reg = <0x20038000 0x100>;
		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
		clock-names = "timer", "pclk";
	};

	timer@2003a000 {
		compatible = "snps,dw-apb-timer-osc";
		reg = <0x2003a000 0x100>;
		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
		clock-names = "timer", "pclk";
	};

	tsadc: tsadc@20060000 {
		compatible = "rockchip,rk3066-tsadc";
		reg = <0x20060000 0x100>;
		clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
		clock-names = "saradc", "apb_pclk";
		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
		#io-channel-cells = <1>;
		resets = <&cru SRST_TSADC>;
		reset-names = "saradc-apb";
		status = "disabled";
	};

	usbphy: phy {
		compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy";
		rockchip,grf = <&grf>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";

		usbphy0: usb-phy@17c {
			#phy-cells = <0>;
			reg = <0x17c>;
			clocks = <&cru SCLK_OTGPHY0>;
			clock-names = "phyclk";
			#clock-cells = <0>;
		};

		usbphy1: usb-phy@188 {
			#phy-cells = <0>;
			reg = <0x188>;
			clocks = <&cru SCLK_OTGPHY1>;
			clock-names = "phyclk";
			#clock-cells = <0>;
		};
	};

	pinctrl: pinctrl {
		compatible = "rockchip,rk3066a-pinctrl";
		rockchip,grf = <&grf>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		gpio0: gpio0@20034000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x20034000 0x100>;
			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO0>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio1: gpio1@2003c000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x2003c000 0x100>;
			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO1>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio2@2003e000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x2003e000 0x100>;
			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO2>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio3@20080000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x20080000 0x100>;
			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO3>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio4: gpio4@20084000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x20084000 0x100>;
			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO4>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio6: gpio6@2000a000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x2000a000 0x100>;
			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO6>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		pcfg_pull_default: pcfg_pull_default {
			bias-pull-pin-default;
		};

		pcfg_pull_none: pcfg_pull_none {
			bias-disable;
		};

		emac {
			emac_xfer: emac-xfer {
				rockchip,pins = <RK_GPIO1 16 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
						<RK_GPIO1 17 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
						<RK_GPIO1 18 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
						<RK_GPIO1 19 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
						<RK_GPIO1 20 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
						<RK_GPIO1 21 RK_FUNC_2 &pcfg_pull_none>, /* crs_dvalid */
						<RK_GPIO1 22 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
						<RK_GPIO1 23 RK_FUNC_2 &pcfg_pull_none>; /* rxd0 */
			};

			emac_mdio: emac-mdio {
				rockchip,pins = <RK_GPIO1 24 RK_FUNC_2 &pcfg_pull_none>, /* mac_md */
						<RK_GPIO1 25 RK_FUNC_2 &pcfg_pull_none>; /* mac_mdclk */
			};
		};

		emmc {
			emmc_clk: emmc-clk {
				rockchip,pins = <RK_GPIO3 31 RK_FUNC_2 &pcfg_pull_default>;
			};

			emmc_cmd: emmc-cmd {
				rockchip,pins = <RK_GPIO4 9 RK_FUNC_2 &pcfg_pull_default>;
			};

			emmc_rst: emmc-rst {
				rockchip,pins = <RK_GPIO4 10 RK_FUNC_2 &pcfg_pull_default>;
			};

			/*
			 * The data pins are shared between nandc and emmc and
			 * not accessible through pinctrl. Also they should've
			 * been already set correctly by firmware, as
			 * flash/emmc is the boot-device.
			 */
		};

		i2c0 {
			i2c0_xfer: i2c0-xfer {
				rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO2 29 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2c1 {
			i2c1_xfer: i2c1-xfer {
				rockchip,pins = <RK_GPIO2 30 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO2 31 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2c2 {
			i2c2_xfer: i2c2-xfer {
				rockchip,pins = <RK_GPIO3 0 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2c3 {
			i2c3_xfer: i2c3-xfer {
				rockchip,pins = <RK_GPIO3 2 RK_FUNC_2 &pcfg_pull_none>,
						<RK_GPIO3 3 RK_FUNC_2 &pcfg_pull_none>;
			};
		};

		i2c4 {
			i2c4_xfer: i2c4-xfer {
				rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pwm0 {
			pwm0_out: pwm0-out {
				rockchip,pins = <RK_GPIO0 3 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pwm1 {
			pwm1_out: pwm1-out {
				rockchip,pins = <RK_GPIO0 4 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pwm2 {
			pwm2_out: pwm2-out {
				rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pwm3 {
			pwm3_out: pwm3-out {
				rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		spi0 {
			spi0_clk: spi0-clk {
				rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_default>;
			};
			spi0_cs0: spi0-cs0 {
				rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_default>;
			};
			spi0_tx: spi0-tx {
				rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_default>;
			};
			spi0_rx: spi0-rx {
				rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_default>;
			};
			spi0_cs1: spi0-cs1 {
				rockchip,pins = <RK_GPIO4 15 RK_FUNC_1 &pcfg_pull_default>;
			};
		};

		spi1 {
			spi1_clk: spi1-clk {
				rockchip,pins = <RK_GPIO2 19 RK_FUNC_2 &pcfg_pull_default>;
			};
			spi1_cs0: spi1-cs0 {
				rockchip,pins = <RK_GPIO2 20 RK_FUNC_2 &pcfg_pull_default>;
			};
			spi1_rx: spi1-rx {
				rockchip,pins = <RK_GPIO2 22 RK_FUNC_2 &pcfg_pull_default>;
			};
			spi1_tx: spi1-tx {
				rockchip,pins = <RK_GPIO2 21 RK_FUNC_2 &pcfg_pull_default>;
			};
			spi1_cs1: spi1-cs1 {
				rockchip,pins = <RK_GPIO2 23 RK_FUNC_2 &pcfg_pull_default>;
			};
		};

		uart0 {
			uart0_xfer: uart0-xfer {
				rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
			};

			uart0_cts: uart0-cts {
				rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
			};

			uart0_rts: uart0-rts {
				rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
			};
		};

		uart1 {
			uart1_xfer: uart1-xfer {
				rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
			};

			uart1_cts: uart1-cts {
				rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
			};

			uart1_rts: uart1-rts {
				rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
			};
		};

		uart2 {
			uart2_xfer: uart2-xfer {
				rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
			};
			/* no rts / cts for uart2 */
		};

		uart3 {
			uart3_xfer: uart3-xfer {
				rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
			};

			uart3_cts: uart3-cts {
				rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
			};

			uart3_rts: uart3-rts {
				rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
			};
		};

		sd0 {
			sd0_clk: sd0-clk {
				rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd0_cmd: sd0-cmd {
				rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd0_cd: sd0-cd {
				rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd0_wp: sd0-wp {
				rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd0_bus1: sd0-bus-width1 {
				rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd0_bus4: sd0-bus-width4 {
				rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
			};
		};

		sd1 {
			sd1_clk: sd1-clk {
				rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd1_cmd: sd1-cmd {
				rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd1_cd: sd1-cd {
				rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd1_wp: sd1-wp {
				rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd1_bus1: sd1-bus-width1 {
				rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd1_bus4: sd1-bus-width4 {
				rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
			};
		};

		i2s0 {
			i2s0_bus: i2s0-bus {
				rockchip,pins = <RK_GPIO0 7 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 8 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 9 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 10 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 11 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 12 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 13 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 14 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 15 RK_FUNC_1 &pcfg_pull_default>;
			};
		};

		i2s1 {
			i2s1_bus: i2s1-bus {
				rockchip,pins = <RK_GPIO0 16 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 17 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 18 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 19 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 20 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 21 RK_FUNC_1 &pcfg_pull_default>;
			};
		};

		i2s2 {
			i2s2_bus: i2s2-bus {
				rockchip,pins = <RK_GPIO0 24 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 25 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 26 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 27 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_default>;
			};
		};
	};
};

&gpu {
	compatible = "rockchip,rk3066-mali", "arm,mali-400";
	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "gp",
			  "gpmmu",
			  "pp0",
			  "ppmmu0",
			  "pp1",
			  "ppmmu1",
			  "pp2",
			  "ppmmu2",
			  "pp3",
			  "ppmmu3";
	power-domains = <&power RK3066_PD_GPU>;
};

&i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_xfer>;
};

&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_xfer>;
};

&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_xfer>;
};

&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c3_xfer>;
};

&i2c4 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c4_xfer>;
};

&mmc0 {
	clock-frequency = <50000000>;
	dmas = <&dmac2 1>;
	dma-names = "rx-tx";
	max-frequency = <50000000>;
	pinctrl-names = "default";
	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
};

&mmc1 {
	dmas = <&dmac2 3>;
	dma-names = "rx-tx";
	pinctrl-names = "default";
	pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
};

&emmc {
	dmas = <&dmac2 4>;
	dma-names = "rx-tx";
};

&pmu {
	power: power-controller {
		compatible = "rockchip,rk3066-power-controller";
		#power-domain-cells = <1>;
		#address-cells = <1>;
		#size-cells = <0>;

		pd_vio@RK3066_PD_VIO {
			reg = <RK3066_PD_VIO>;
			clocks = <&cru ACLK_LCDC0>,
				 <&cru ACLK_LCDC1>,
				 <&cru DCLK_LCDC0>,
				 <&cru DCLK_LCDC1>,
				 <&cru HCLK_LCDC0>,
				 <&cru HCLK_LCDC1>,
				 <&cru SCLK_CIF1>,
				 <&cru ACLK_CIF1>,
				 <&cru HCLK_CIF1>,
				 <&cru SCLK_CIF0>,
				 <&cru ACLK_CIF0>,
				 <&cru HCLK_CIF0>,
				 <&cru HCLK_HDMI>,
				 <&cru ACLK_IPP>,
				 <&cru HCLK_IPP>,
				 <&cru ACLK_RGA>,
				 <&cru HCLK_RGA>;
			pm_qos = <&qos_lcdc0>,
				 <&qos_lcdc1>,
				 <&qos_cif0>,
				 <&qos_cif1>,
				 <&qos_ipp>,
				 <&qos_rga>;
		};

		pd_video@RK3066_PD_VIDEO {
			reg = <RK3066_PD_VIDEO>;
			clocks = <&cru ACLK_VDPU>,
				 <&cru ACLK_VEPU>,
				 <&cru HCLK_VDPU>,
				 <&cru HCLK_VEPU>;
			pm_qos = <&qos_vpu>;
		};

		pd_gpu@RK3066_PD_GPU {
			reg = <RK3066_PD_GPU>;
			clocks = <&cru ACLK_GPU>;
			pm_qos = <&qos_gpu>;
		};
	};
};

&pwm0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm0_out>;
};

&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm1_out>;
};

&pwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm2_out>;
};

&pwm3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm3_out>;
};

&spi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
};

&spi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
};

&uart0 {
	compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
	dmas = <&dmac1_s 0>, <&dmac1_s 1>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_xfer>;
};

&uart1 {
	compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
	dmas = <&dmac1_s 2>, <&dmac1_s 3>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_xfer>;
};

&uart2 {
	compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
	dmas = <&dmac2 6>, <&dmac2 7>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_xfer>;
};

&uart3 {
	compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
	dmas = <&dmac2 8>, <&dmac2 9>;
	dma-names = "tx", "rx";
	pinctrl-names = "default";
	pinctrl-0 = <&uart3_xfer>;
};

&wdt {
	compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
};

&emac {
	compatible = "rockchip,rk3066-emac";
};