1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-netx/nxeb500hmi.c
*
* Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
*/
#include <linux/dma-mapping.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/mtd/plat-ram.h>
#include <linux/platform_device.h>
#include <linux/amba/bus.h>
#include <linux/amba/clcd.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/netx-regs.h>
#include <linux/platform_data/eth-netx.h>
#include "generic.h"
#include "fb.h"
static struct clcd_panel qvga = {
.mode = {
.name = "QVGA",
.refresh = 60,
.xres = 240,
.yres = 320,
.pixclock = 187617,
.left_margin = 6,
.right_margin = 26,
.upper_margin = 0,
.lower_margin = 6,
.hsync_len = 6,
.vsync_len = 1,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED,
},
.width = -1,
.height = -1,
.tim2 = 16,
.cntl = CNTL_LCDTFT | CNTL_BGR,
.bpp = 16,
.grayscale = 0,
};
static inline int nxeb500hmi_check(struct clcd_fb *fb, struct fb_var_screeninfo *var)
{
var->green.length = 5;
var->green.msb_right = 0;
return clcdfb_check(fb, var);
}
static int nxeb500hmi_clcd_setup(struct clcd_fb *fb)
{
unsigned int val;
fb->fb.var.green.length = 5;
fb->fb.var.green.msb_right = 0;
/* enable asic control */
val = readl(NETX_SYSTEM_IOC_ACCESS_KEY);
writel(val, NETX_SYSTEM_IOC_ACCESS_KEY);
writel(3, NETX_SYSTEM_IOC_CR);
/* GPIO 14 is used for display enable on newer boards */
writel(9, NETX_GPIO_CFG(14));
val = readl(NETX_PIO_OUTPIO);
writel(val | 1, NETX_PIO_OUTPIO);
val = readl(NETX_PIO_OEPIO);
writel(val | 1, NETX_PIO_OEPIO);
return netx_clcd_setup(fb);
}
static struct clcd_board clcd_data = {
.name = "netX",
.check = nxeb500hmi_check,
.decode = clcdfb_decode,
.enable = netx_clcd_enable,
.setup = nxeb500hmi_clcd_setup,
.mmap = netx_clcd_mmap,
.remove = netx_clcd_remove,
};
static struct netxeth_platform_data eth0_platform_data = {
.xcno = 0,
};
static struct platform_device netx_eth0_device = {
.name = "netx-eth",
.id = 0,
.num_resources = 0,
.resource = NULL,
.dev = {
.platform_data = ð0_platform_data,
}
};
static struct netxeth_platform_data eth1_platform_data = {
.xcno = 1,
};
static struct platform_device netx_eth1_device = {
.name = "netx-eth",
.id = 1,
.num_resources = 0,
.resource = NULL,
.dev = {
.platform_data = ð1_platform_data,
}
};
static struct resource netx_cf_resources[] = {
[0] = {
.start = 0x20000000,
.end = 0x25ffffff,
.flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
},
};
static struct platform_device netx_cf_device = {
.name = "netx-cf",
.id = 0,
.resource = netx_cf_resources,
.num_resources = ARRAY_SIZE(netx_cf_resources),
};
static struct resource netx_uart0_resources[] = {
[0] = {
.start = 0x00100A00,
.end = 0x00100A3F,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = (NETX_IRQ_UART0),
.end = (NETX_IRQ_UART0),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device netx_uart0_device = {
.name = "netx-uart",
.id = 0,
.num_resources = ARRAY_SIZE(netx_uart0_resources),
.resource = netx_uart0_resources,
};
static struct platform_device *devices[] __initdata = {
&netx_eth0_device,
&netx_eth1_device,
&netx_cf_device,
&netx_uart0_device,
};
static void __init nxeb500hmi_init(void)
{
netx_fb_init(&clcd_data, &qvga);
platform_add_devices(devices, ARRAY_SIZE(devices));
}
MACHINE_START(NXEB500HMI, "Hilscher nxeb500hmi")
.atag_offset = 0x100,
.map_io = netx_map_io,
.init_irq = netx_init_irq,
.init_time = netx_timer_init,
.init_machine = nxeb500hmi_init,
.restart = netx_restart,
MACHINE_END
|
