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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2014-01-07 16:14:09 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-01-07 22:21:01 +0100 |
| commit | 03dce881292f43b269f1f8acca69df2c4568ee5c (patch) | |
| tree | 6f151a67363cf4d5a162b8df7fd50dbd1a02171b | |
| parent | a42a57196ad897e7686944488b23f5d2b6496372 (diff) | |
| download | linux-03dce881292f43b269f1f8acca69df2c4568ee5c.tar.gz linux-03dce881292f43b269f1f8acca69df2c4568ee5c.tar.bz2 linux-03dce881292f43b269f1f8acca69df2c4568ee5c.zip | |
drm/i915: Enable watermarks for BDW
We forgot to intialize the watermark vfuncs for BDW, and hence the
watermarks were never updated.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 78503157daf2..835f86386b95 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5627,6 +5627,17 @@ void intel_init_pm(struct drm_device *dev) } dev_priv->display.init_clock_gating = haswell_init_clock_gating; } else if (INTEL_INFO(dev)->gen == 8) { + if (dev_priv->wm.pri_latency[0] && + dev_priv->wm.spr_latency[0] && + dev_priv->wm.cur_latency[0]) { + dev_priv->display.update_wm = ilk_update_wm; + dev_priv->display.update_sprite_wm = + ilk_update_sprite_wm; + } else { + DRM_DEBUG_KMS("Failed to read display plane latency. " + "Disable CxSR\n"); + dev_priv->display.update_wm = NULL; + } dev_priv->display.init_clock_gating = gen8_init_clock_gating; } else dev_priv->display.update_wm = NULL; |