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authorHoath, Nicholas <nicholas.hoath@intel.com>2015-02-05 10:47:24 +0000
committerDaniel Vetter <daniel.vetter@ffwll.ch>2015-02-13 23:28:10 +0100
commit13bea49c8b203b0d2eb789c6f91c03de4e09cf4d (patch)
tree6bd73899b75fa6cb01c7e7fb8372853af228fe41
parent1840481f536b40289b61c13f9111f30f4019e5ff (diff)
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drm/i915/gen9: Implement WaForceEnableNonCoherent
v2: Don't add WaHdcDisableFetchWhenMasked. Add stepping check for WaForceEnableNonCoherent Signed-off-by: Nick Hoath <nicholas.hoath@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index e35b341c3cef..573b80f0c153 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -902,6 +902,17 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
GEN9_ENABLE_YV12_BUGFIX);
}
+ if (INTEL_REVID(dev) <= SKL_REVID_D0) {
+ /*
+ *Use Force Non-Coherent whenever executing a 3D context. This
+ * is a workaround for a possible hang in the unlikely event
+ * a TLB invalidation occurs during a PSD flush.
+ */
+ /* WaForceEnableNonCoherent:skl */
+ WA_SET_BIT_MASKED(HDC_CHICKEN0,
+ HDC_FORCE_NON_COHERENT);
+ }
+
/* Wa4x4STCOptimizationDisable:skl */
WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);