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authorMike Turquette <mturquette@ti.com>2011-10-07 00:53:00 -0600
committerPaul Walmsley <paul@pwsan.com>2011-10-07 00:53:00 -0600
commit273a1ce9cf27ac3900325b59aa78cc07bb574e9e (patch)
tree1ee164c1b02a17b04858a5132317ad9b721cd2f9
parentaddf888c6945c6e3cff135e7e3bb72cc708d1ca4 (diff)
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ARM: OMAP3+: dpll: assign clk rate from rounded rate during rate set
The rounded rate can differ from target rate, so to better reflect reality set clk->rate equal to the rounded rate when setting DPLL frequency. This avoids issues where the DPLL frequency is slightly different than what debugfs clock tree reports using the old target rate. An example of a clock that requires this is DPLL_ABE on OMAP4 which can have a 4x multiplier on top of the usual MN dividers depending on register settings. This requires a special round_rate function that might yield a rate different from the initial target. Signed-off-by: Mike Turquette <mturquette@ti.com> Signed-off-by: Jon Hunter <jon-hunter@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
-rw-r--r--arch/arm/mach-omap2/dpll3xxx.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index 6b0fa3786022..73a1595c5f21 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -455,7 +455,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
new_parent = dd->clk_bypass;
} else {
if (dd->last_rounded_rate != rate)
- clk->round_rate(clk, rate);
+ rate = clk->round_rate(clk, rate);
if (dd->last_rounded_rate == 0)
return -EINVAL;