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| author | Tobias Schramm <t.schramm@manjaro.org> | 2020-08-15 00:35:43 +0200 |
|---|---|---|
| committer | Alexandre Torgue <alexandre.torgue@st.com> | 2020-09-23 18:37:02 +0200 |
| commit | 33aa48808619393d70f103da85db03847f29b90f (patch) | |
| tree | 79f054b1f7d37a56e9757d67b1bde8e72b11d6ad | |
| parent | 9fc37291831fd85e579cacccb3d887c4f240f2e8 (diff) | |
| download | linux-33aa48808619393d70f103da85db03847f29b90f.tar.gz linux-33aa48808619393d70f103da85db03847f29b90f.tar.bz2 linux-33aa48808619393d70f103da85db03847f29b90f.zip | |
ARM: dts: stm32: add resets property to spi device nodes on stm32h743
The stm32 spi driver tries to determine the fifo size of spi devices
dynamically. However, if the spi was already configured by the bootloader
the fifo size check can become an endless loop, because the driver
expects the spi to be in its initial "after device reset" state. The
driver does already support resetting the spi device at probe, thus this
patch adds only the required device tree properties
Signed-off-by: Tobias Schramm <t.schramm@manjaro.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
| -rw-r--r-- | arch/arm/boot/dts/stm32h743.dtsi | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi index 2ac6e17c7035..59995720c270 100644 --- a/arch/arm/boot/dts/stm32h743.dtsi +++ b/arch/arm/boot/dts/stm32h743.dtsi @@ -110,6 +110,7 @@ compatible = "st,stm32h7-spi"; reg = <0x40003800 0x400>; interrupts = <36>; + resets = <&rcc STM32H7_APB1L_RESET(SPI2)>; clocks = <&rcc SPI2_CK>; status = "disabled"; @@ -121,6 +122,7 @@ compatible = "st,stm32h7-spi"; reg = <0x40003c00 0x400>; interrupts = <51>; + resets = <&rcc STM32H7_APB1L_RESET(SPI3)>; clocks = <&rcc SPI3_CK>; status = "disabled"; }; @@ -207,6 +209,7 @@ compatible = "st,stm32h7-spi"; reg = <0x40013000 0x400>; interrupts = <35>; + resets = <&rcc STM32H7_APB2_RESET(SPI1)>; clocks = <&rcc SPI1_CK>; status = "disabled"; }; @@ -217,6 +220,7 @@ compatible = "st,stm32h7-spi"; reg = <0x40013400 0x400>; interrupts = <84>; + resets = <&rcc STM32H7_APB2_RESET(SPI4)>; clocks = <&rcc SPI4_CK>; status = "disabled"; }; @@ -227,6 +231,7 @@ compatible = "st,stm32h7-spi"; reg = <0x40015000 0x400>; interrupts = <85>; + resets = <&rcc STM32H7_APB2_RESET(SPI5)>; clocks = <&rcc SPI5_CK>; status = "disabled"; }; @@ -382,6 +387,7 @@ compatible = "st,stm32h7-spi"; reg = <0x58001400 0x400>; interrupts = <86>; + resets = <&rcc STM32H7_APB4_RESET(SPI6)>; clocks = <&rcc SPI6_CK>; status = "disabled"; }; |