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| author | Nicolas Frattaroli <frattaroli.nicolas@gmail.com> | 2022-11-12 17:04:01 +0100 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2022-11-15 11:46:15 +0100 |
| commit | 3736aa7ecc4cd9b4abce30052bad00aba4f0362f (patch) | |
| tree | 84f11b905e1644ded70705b2f1983008e7f51ddd | |
| parent | 70b620c4ba919a87c607b8d98b08478b213877bd (diff) | |
| download | linux-3736aa7ecc4cd9b4abce30052bad00aba4f0362f.tar.gz linux-3736aa7ecc4cd9b4abce30052bad00aba4f0362f.tar.bz2 linux-3736aa7ecc4cd9b4abce30052bad00aba4f0362f.zip | |
arm64: dts: rockchip: Enable PCIe 2 on SOQuartz CM4IO
This patch enables the PCIe2 on the CM4IO board when paired with
a SOQuartz CM4 System-on-Module board. combphy2 also needs to be
enabled in this case to make the PHY work for this.
Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
Link: https://lore.kernel.org/r/20221112160404.70868-5-frattaroli.nicolas@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts | 11 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi | 15 |
2 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts index e00568a6be5c..263ce40770dd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts @@ -30,6 +30,12 @@ }; }; +/* phy for pcie */ +&combphy2 { + phy-supply = <&vcc3v3_sys>; + status = "okay"; +}; + &gmac1 { status = "okay"; }; @@ -105,6 +111,11 @@ status = "okay"; }; +&pcie2x1 { + vpcie3v3-supply = <&vcc_3v3>; + status = "okay"; +}; + &rgmii_phy1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi index 1b975822effa..ce7165d7f1a1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi @@ -487,6 +487,12 @@ }; }; +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset_h>; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; +}; + &pinctrl { bt { bt_enable_h: bt-enable-h { @@ -512,6 +518,15 @@ }; }; + pcie { + pcie_clkreq_h: pcie-clkreq-h { + rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + pcie_reset_h: pcie-reset-h { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pmic { pmic_int_l: pmic-int-l { rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; |