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| author | Andrzej Hajda <andrzej.hajda@intel.com> | 2023-09-12 09:35:21 +0200 |
|---|---|---|
| committer | Andrzej Hajda <andrzej.hajda@intel.com> | 2023-09-13 12:17:56 +0200 |
| commit | 3b2562dcf91d460753871415f9571effc7965fcf (patch) | |
| tree | 92e827447789db32ed8e853e71f5a52ea7ec29d9 | |
| parent | c795d2f40a29f3aa9a4ed811f7787bf2f78111f4 (diff) | |
| download | linux-3b2562dcf91d460753871415f9571effc7965fcf.tar.gz linux-3b2562dcf91d460753871415f9571effc7965fcf.tar.bz2 linux-3b2562dcf91d460753871415f9571effc7965fcf.zip | |
drm/i915/gt: skip WA verification for GEN7_MISCCPCTL on DG2
Some DG2 firmware locks this register for modification. Using wa_add
with read_mask 0 allows to skip checks of such registers.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8945
Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230912073521.2106162-1-andrzej.hajda@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index e950efc75983..fcde2e1562ab 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1596,8 +1596,12 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) /* Wa_14014830051:dg2 */ wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN); - /* Wa_14015795083 */ - wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); + /* + * Wa_14015795083 + * Skip verification for possibly locked register. + */ + wa_add(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE, + 0, 0, false); /* Wa_18018781329 */ wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); |