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| author | Palmer Dabbelt <palmer@sifive.com> | 2018-10-02 12:14:55 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2018-10-22 17:03:35 -0700 |
| commit | 566d6c428eadf9dc06df8b2195dff58d9a97c9e6 (patch) | |
| tree | 026f0ab6a209ce19657e83d9dd7114cf9e438b30 | |
| parent | 1ed4237ab616a05225e11d07bf42d5474deec905 (diff) | |
| download | linux-566d6c428eadf9dc06df8b2195dff58d9a97c9e6.tar.gz linux-566d6c428eadf9dc06df8b2195dff58d9a97c9e6.tar.bz2 linux-566d6c428eadf9dc06df8b2195dff58d9a97c9e6.zip | |
RISC-V: Don't set cacheinfo.{physical_line_partition,attributes}
These are just hard coded in the RISC-V port, which doesn't make any
sense. We should probably be setting these from device tree entries
when they exist, but for now I think it's saner to just leave them all
as their default values.
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Jeremy Linton <jeremy.linton@arm.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| -rw-r--r-- | arch/riscv/kernel/cacheinfo.c | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c index 0bc86e5f8f3f..cb35ffd8ec6b 100644 --- a/arch/riscv/kernel/cacheinfo.c +++ b/arch/riscv/kernel/cacheinfo.c @@ -22,13 +22,6 @@ static void ci_leaf_init(struct cacheinfo *this_leaf, { this_leaf->level = level; this_leaf->type = type; - /* not a sector cache */ - this_leaf->physical_line_partition = 1; - /* TODO: Add to DTS */ - this_leaf->attributes = - CACHE_WRITE_BACK - | CACHE_READ_ALLOCATE - | CACHE_WRITE_ALLOCATE; } static int __init_cache_level(unsigned int cpu) |