diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2021-07-15 12:35:19 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2021-08-25 17:05:39 +0300 |
| commit | 6501e6bb1458c2e61b0158625518c19bef9c7dce (patch) | |
| tree | 39020fe23135b19277334ba73e569adb35873b43 | |
| parent | 35a17f93e03a1f69f7a869c90f6f5c3ba75228e3 (diff) | |
| download | linux-6501e6bb1458c2e61b0158625518c19bef9c7dce.tar.gz linux-6501e6bb1458c2e61b0158625518c19bef9c7dce.tar.bz2 linux-6501e6bb1458c2e61b0158625518c19bef9c7dce.zip | |
drm/i915: Clean up gen2 DPLL readout
The current gen2 DPLL readout code:
* assumes i845/i865 have LVDS which is not true
* assumes only pipe B can drive LVDS (true, but makes
the code appear a bit magical)
* hard to parse in general
Clean it up by checking for i85x (the only gen2 platform
with LVDS) and reusing intel_lvds_port_enabled().
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210715093530.31711-3-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_display.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 794690c0dba5..13a92a3acb73 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -6319,7 +6319,6 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc, { struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); - enum pipe pipe = crtc->pipe; u32 dpll = pipe_config->dpll_hw_state.dpll; u32 fp; struct dpll clock; @@ -6369,11 +6368,13 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc, else port_clock = i9xx_calc_dpll_params(refclk, &clock); } else { - u32 lvds = IS_I830(dev_priv) ? 0 : intel_de_read(dev_priv, - LVDS); - bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); + enum pipe lvds_pipe; + + if (IS_I85X(dev_priv) && + intel_lvds_port_enabled(dev_priv, LVDS, &lvds_pipe) && + lvds_pipe == crtc->pipe) { + u32 lvds = intel_de_read(dev_priv, LVDS); - if (is_lvds) { clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> DPLL_FPA01_P1_POST_DIV_SHIFT); |