diff options
| author | Isabel Zhang <isabel.zhang@amd.com> | 2020-10-16 10:55:54 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-11-02 15:29:59 -0500 |
| commit | 685b4d8142dcbf11b817f74c2bc5b94eca7ee7f2 (patch) | |
| tree | c935b66c392d02b88a382e95d208f5b4b5784cc4 | |
| parent | 850d2fcf3e346a35e4e59e310b867e90e3ef8e5a (diff) | |
| download | linux-685b4d8142dcbf11b817f74c2bc5b94eca7ee7f2.tar.gz linux-685b4d8142dcbf11b817f74c2bc5b94eca7ee7f2.tar.bz2 linux-685b4d8142dcbf11b817f74c2bc5b94eca7ee7f2.zip | |
drm/amd/display: Force prefetch mode to 0
[Why]
On APU should be always using prefetch mode 0.
Currently, sometimes prefetch mode 1 is being
used causing system to hard hang due to
minTTUVBlank being too low.
[How]
Any ASIC running DCN21 will by default allow
self refresh and mclk switch. This sets both
min and max prefetch mode to 0 by default.
Signed-off-by: Isabel Zhang <isabel.zhang@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c index 70a18271bd2d..5ae3419682c8 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c @@ -301,7 +301,9 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = { .xfc_bus_transport_time_us = 4, .xfc_xbuf_latency_tolerance_us = 4, .use_urgent_burst_bw = 1, - .num_states = 8 + .num_states = 8, + .allow_dram_self_refresh_or_dram_clock_change_in_vblank + = dm_allow_self_refresh_and_mclk_switch }; #ifndef MAX |