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| author | Lucas De Marchi <lucas.demarchi@intel.com> | 2023-01-20 11:34:53 -0800 |
|---|---|---|
| committer | Lucas De Marchi <lucas.demarchi@intel.com> | 2023-01-27 08:52:20 -0800 |
| commit | 7b775d36589390eaf19ceada78141c60ed1c7c84 (patch) | |
| tree | d4c515c437b3c016c4386339a8c809580f3d70e8 | |
| parent | 680d0c7960f12fc3852c70b2bab278cc5e70b88a (diff) | |
| download | linux-7b775d36589390eaf19ceada78141c60ed1c7c84.tar.gz linux-7b775d36589390eaf19ceada78141c60ed1c7c84.tar.bz2 linux-7b775d36589390eaf19ceada78141c60ed1c7c84.zip | |
drm/i915: Replace _MMIO_PHY3() with _PICK_EVEN_2RANGES()
As done previously for pll, also convert users of _PHY3() to
_PICK_EVEN_2RANGES(). Size comparison of i915.o:
$ size build64/drivers/gpu/drm/i915/i915.o{.old,.new}
text data bss dec hex filename
4026997 185703 6984 4219684 406324 build64/drivers/gpu/drm/i915/i915.o.old
4026288 185703 6984 4218975 40605f build64/drivers/gpu/drm/i915/i915.o.new
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230120193457.3295977-5-lucas.demarchi@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_display_reg_defs.h | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 16 |
2 files changed, 9 insertions, 10 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h index a4ed1c530799..f1681e1396b5 100644 --- a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h +++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h @@ -29,11 +29,8 @@ #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b)) #define _MMIO_PHY(phy, a, b) _MMIO(_PHY(phy, a, b)) -#define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__) - #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) -#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c)) /* * Device info offset array based helpers for groups of registers with unevenly diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2f224db27095..d63d735ee3af 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -541,9 +541,10 @@ #define _BXT_PHY0_BASE 0x6C000 #define _BXT_PHY1_BASE 0x162000 #define _BXT_PHY2_BASE 0x163000 -#define BXT_PHY_BASE(phy) _PHY3((phy), _BXT_PHY0_BASE, \ - _BXT_PHY1_BASE, \ - _BXT_PHY2_BASE) +#define BXT_PHY_BASE(phy) \ + _PICK_EVEN_2RANGES(phy, 1, \ + _BXT_PHY0_BASE, _BXT_PHY0_BASE, \ + _BXT_PHY1_BASE, _BXT_PHY2_BASE) #define _BXT_PHY(phy, reg) \ _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg)) @@ -566,13 +567,14 @@ #define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \ _BXT_PHY_CTL_DDI_B) -#define _PHY_CTL_FAMILY_EDP 0x64C80 #define _PHY_CTL_FAMILY_DDI 0x64C90 +#define _PHY_CTL_FAMILY_EDP 0x64C80 #define _PHY_CTL_FAMILY_DDI_C 0x64CA0 #define COMMON_RESET_DIS (1 << 31) -#define BXT_PHY_CTL_FAMILY(phy) _MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \ - _PHY_CTL_FAMILY_EDP, \ - _PHY_CTL_FAMILY_DDI_C) +#define BXT_PHY_CTL_FAMILY(phy) \ + _MMIO(_PICK_EVEN_2RANGES(phy, 1, \ + _PHY_CTL_FAMILY_DDI, _PHY_CTL_FAMILY_DDI, \ + _PHY_CTL_FAMILY_EDP, _PHY_CTL_FAMILY_DDI_C)) /* BXT PHY PLL registers */ #define _PORT_PLL_A 0x46074 |