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| author | Alexander Shiyan <shc_work@mail.ru> | 2013-11-08 13:00:22 +0400 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2013-12-09 13:18:30 +0800 |
| commit | 9b015e5a95c54171b72b83e7d4ffb60489d867b4 (patch) | |
| tree | 9dcc7f63ee7436a6ccbb21e3c6dbf00ee5a0ec51 | |
| parent | 5bcaa7a32cd90f7e6fbbbfcbc65b5cdbf12cb8a3 (diff) | |
| download | linux-9b015e5a95c54171b72b83e7d4ffb60489d867b4.tar.gz linux-9b015e5a95c54171b72b83e7d4ffb60489d867b4.tar.bz2 linux-9b015e5a95c54171b72b83e7d4ffb60489d867b4.zip | |
ARM: i.MX5x: Add SAHARA clock for i.MX5x CPUs
Patch adds missing Security Accelerator (SAHARA) clock for i.MX5x CPUs.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| -rw-r--r-- | Documentation/devicetree/bindings/clock/imx5-clock.txt | 1 | ||||
| -rw-r--r-- | arch/arm/mach-imx/clk-imx51-imx53.c | 3 |
2 files changed, 3 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/clock/imx5-clock.txt b/Documentation/devicetree/bindings/clock/imx5-clock.txt index 4c029a8739d3..3716b36c1440 100644 --- a/Documentation/devicetree/bindings/clock/imx5-clock.txt +++ b/Documentation/devicetree/bindings/clock/imx5-clock.txt @@ -198,6 +198,7 @@ clocks and IDs. spdif1_gate 184 spdif_ipg_gate 185 ocram 186 + sahara_ipg_gate 187 Examples (for mx53): diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c index af8fd0861459..3d91172a9554 100644 --- a/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/arch/arm/mach-imx/clk-imx51-imx53.c @@ -122,7 +122,7 @@ enum imx5_clks { srtc_gate, pata_gate, sata_gate, spdif_xtal_sel, spdif0_sel, spdif1_sel, spdif0_pred, spdif0_podf, spdif1_pred, spdif1_podf, spdif0_com_s, spdif1_com_sel, spdif0_gate, spdif1_gate, spdif_ipg_gate, - ocram, clk_max + ocram, sahara_ipg_gate, clk_max }; static struct clk *clk[clk_max]; @@ -285,6 +285,7 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, spdif0_com_sel, ARRAY_SIZE(spdif0_com_sel), CLK_SET_RATE_PARENT); clk[spdif0_gate] = imx_clk_gate2("spdif0_gate", "spdif0_com_sel", MXC_CCM_CCGR5, 26); clk[spdif_ipg_gate] = imx_clk_gate2("spdif_ipg_gate", "ipg", MXC_CCM_CCGR5, 30); + clk[sahara_ipg_gate] = imx_clk_gate2("sahara_ipg_gate", "ipg", MXC_CCM_CCGR4, 14); for (i = 0; i < ARRAY_SIZE(clk); i++) if (IS_ERR(clk[i])) |