diff options
| author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2020-05-12 23:51:47 +0200 |
|---|---|---|
| committer | Kevin Hilman <khilman@baylibre.com> | 2020-05-19 16:18:58 -0700 |
| commit | b632506c5af22a9a7c63674fc605d24cf94d585b (patch) | |
| tree | 9a52722a3e81da49b014e2e6fce8be641b454bb1 | |
| parent | f5a7382d6f176e29e4fd9d733b93d5b93771a7e4 (diff) | |
| download | linux-b632506c5af22a9a7c63674fc605d24cf94d585b.tar.gz linux-b632506c5af22a9a7c63674fc605d24cf94d585b.tar.bz2 linux-b632506c5af22a9a7c63674fc605d24cf94d585b.zip | |
ARM: dts: meson: Add the Ethernet "timing-adjustment" clock
Add the "timing-adjusment" clock now that we now that this is connected
to the PRG_ETHERNET registers. It is used internally to generate the
RGMII RX delay no the MAC side (if needed).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20200512215148.540322-2-martin.blumenstingl@googlemail.com
| -rw-r--r-- | arch/arm/boot/dts/meson8b.dtsi | 5 | ||||
| -rw-r--r-- | arch/arm/boot/dts/meson8m2.dtsi | 5 |
2 files changed, 6 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index e34b039b9357..ba36168b9c1b 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -425,8 +425,9 @@ clocks = <&clkc CLKID_ETH>, <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL2>; - clock-names = "stmmaceth", "clkin0", "clkin1"; + <&clkc CLKID_MPLL2>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment"; rx-fifo-depth = <4096>; tx-fifo-depth = <2048>; diff --git a/arch/arm/boot/dts/meson8m2.dtsi b/arch/arm/boot/dts/meson8m2.dtsi index ca749cc3cc65..2397ba06d608 100644 --- a/arch/arm/boot/dts/meson8m2.dtsi +++ b/arch/arm/boot/dts/meson8m2.dtsi @@ -30,8 +30,9 @@ 0xc1108140 0x8>; clocks = <&clkc CLKID_ETH>, <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL2>; - clock-names = "stmmaceth", "clkin0", "clkin1"; + <&clkc CLKID_MPLL2>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment"; resets = <&reset RESET_ETHERNET>; reset-names = "stmmaceth"; }; |