diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2019-05-02 23:06:07 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2019-05-03 19:22:33 +0300 |
| commit | b7ffc4a839a553b07b34543684e79526f2ffecb8 (patch) | |
| tree | 0acdb4cb8bc2a333eb3a259e8ccc305db33817e1 | |
| parent | a832d35762a0b3e3ad1d4ce8e4dc3915056c853b (diff) | |
| download | linux-b7ffc4a839a553b07b34543684e79526f2ffecb8.tar.gz linux-b7ffc4a839a553b07b34543684e79526f2ffecb8.tar.bz2 linux-b7ffc4a839a553b07b34543684e79526f2ffecb8.zip | |
drm/i915: Allow ICL pipe "HDR mode" when the cursor is visible
Turns out the cursor is compatible with the pipe "HDR mode". It's
only the actual SDR planes that get entirely bypassed during
blending. So let's ignore the cursor when checking if we have
any planes active that aren't HDR compatible. This fixes the
regressions in the kms_cursor_crc and kms_plane_cursor tests.
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110579
Fixes: 09b25812db10 ("drm/i915: Enable pipe HDR mode on ICL if only HDR planes are used")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190502200607.14504-2-ville.syrjala@linux.intel.com
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 45a8c6e3c5cf..b83c238faee1 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -8944,7 +8944,8 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) PIPEMISC_YUV420_MODE_FULL_BLEND; if (INTEL_GEN(dev_priv) >= 11 && - (crtc_state->active_planes & ~icl_hdr_plane_mask()) == 0) + (crtc_state->active_planes & ~(icl_hdr_plane_mask() | + BIT(PLANE_CURSOR))) == 0) val |= PIPEMISC_HDR_MODE_PRECISION; I915_WRITE(PIPEMISC(crtc->pipe), val); |