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authorLorenzo Pieralisi <lorenzo.pieralisi@arm.com>2012-09-07 11:09:15 +0530
committerLorenzo Pieralisi <lorenzo.pieralisi@arm.com>2012-09-25 11:20:26 +0100
commite6b866e954a7f0d0144a951c158f3922dac1e6b9 (patch)
tree9d0cbf02117228da9bda0071f2f949109a16f65b
parentdbee0c6fb4c1269b2dfc8b0b7a29907ea7fed560 (diff)
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ARM: kernel: update __cpu_disable to use cache LoUIS maintenance API
When a CPU is hotplugged out caches that reside in its power domain lose their contents and so must be cleaned to the next memory level. Currently, __cpu_disable calls flush_cache_all() that for new generation processor like A15/A7 ends up cleaning and invalidating all cache levels up to Level of Coherency, which includes the unified L2. This ends up being a waste of cycles since the L2 cache contents are not lost on power down. This patch updates __cpu_disable to use the new LoUIS API cache operations. Acked-by: Nicolas Pitre <nico@linaro.org> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Shawn Guo <shawn.guo@linaro.org>
-rw-r--r--arch/arm/kernel/smp.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index ebd8ad274d76..199558b9462e 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -134,8 +134,11 @@ int __cpu_disable(void)
/*
* Flush user cache and TLB mappings, and then remove this CPU
* from the vm mask set of all processes.
+ *
+ * Caches are flushed to the Level of Unification Inner Shareable
+ * to write-back dirty lines to unified caches shared by all CPUs.
*/
- flush_cache_all();
+ flush_cache_louis();
local_flush_tlb_all();
clear_tasks_mm_cpumask(cpu);