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author | Wolfram Sang <wsa+renesas@sang-engineering.com> | 2022-10-06 21:04:50 +0200 |
---|---|---|
committer | Ulf Hansson <ulf.hansson@linaro.org> | 2022-12-07 13:22:36 +0100 |
commit | ec9e80ae1719de541c719116a1ca0a0c70e9240c (patch) | |
tree | bbfdb6e1afde22fe228229e8400c1361944a396b | |
parent | af728d7ae20483add9f8d3c81280dc6298a0aa2e (diff) | |
download | linux-ec9e80ae1719de541c719116a1ca0a0c70e9240c.tar.gz linux-ec9e80ae1719de541c719116a1ca0a0c70e9240c.tar.bz2 linux-ec9e80ae1719de541c719116a1ca0a0c70e9240c.zip |
mmc: renesas_sdhi: add quirk for broken register layout
Some early Gen3 SoCs have the DTRANEND1 bit at a different location than
all later SoCs. Because we need the bit soon, add a quirk so we know
which bit to use.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: Duy Nguyen <duy.nguyen.rh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20221006190452.5316-5-wsa+renesas@sang-engineering.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
-rw-r--r-- | drivers/mmc/host/renesas_sdhi.h | 1 | ||||
-rw-r--r-- | drivers/mmc/host/renesas_sdhi_internal_dmac.c | 4 |
2 files changed, 4 insertions, 1 deletions
diff --git a/drivers/mmc/host/renesas_sdhi.h b/drivers/mmc/host/renesas_sdhi.h index b661892847f6..fa88b721364c 100644 --- a/drivers/mmc/host/renesas_sdhi.h +++ b/drivers/mmc/host/renesas_sdhi.h @@ -44,6 +44,7 @@ struct renesas_sdhi_quirks { bool fixed_addr_mode; bool dma_one_rx_only; bool manual_tap_correction; + bool old_info1_layout; u32 hs400_bad_taps; const u8 (*hs400_calib_table)[SDHI_CALIB_TABLE_MAX]; }; diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/host/renesas_sdhi_internal_dmac.c index 48bea0bd75e8..630ec1e785d6 100644 --- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c +++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c @@ -49,7 +49,8 @@ /* DM_CM_INFO1 and DM_CM_INFO1_MASK */ #define INFO1_CLEAR 0 #define INFO1_MASK_CLEAR GENMASK_ULL(31, 0) -#define INFO1_DTRANEND1 BIT(17) +#define INFO1_DTRANEND1 BIT(20) +#define INFO1_DTRANEND1_OLD BIT(17) #define INFO1_DTRANEND0 BIT(16) /* DM_CM_INFO2 and DM_CM_INFO2_MASK */ @@ -165,6 +166,7 @@ static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400_one_rx = { .hs400_disabled = true, .hs400_4taps = true, .dma_one_rx_only = true, + .old_info1_layout = true, }; static const struct renesas_sdhi_quirks sdhi_quirks_4tap = { |