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| author | Peter Ujfalusi <peter.ujfalusi@ti.com> | 2013-06-24 15:42:04 +0200 |
|---|---|---|
| committer | Mark Brown <broonie@linaro.org> | 2013-06-24 16:05:58 +0100 |
| commit | fa223ec37c9f6710022381a25c352955675817f9 (patch) | |
| tree | f5663187645d068b554b4be599ef8ae34d3a4605 | |
| parent | f60596d61fc238befd169ea394ba6a458fafd774 (diff) | |
| download | linux-fa223ec37c9f6710022381a25c352955675817f9.tar.gz linux-fa223ec37c9f6710022381a25c352955675817f9.tar.bz2 linux-fa223ec37c9f6710022381a25c352955675817f9.zip | |
mfd: twl6040: Update register bit definitions
Add define for: HSDRV, HFDAC, HFPGA and HFDRV enable bits
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
CC: Samuel Ortiz <sameo@linux.intel.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
| -rw-r--r-- | include/linux/mfd/twl6040.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/include/linux/mfd/twl6040.h b/include/linux/mfd/twl6040.h index 94ac944d12f0..7e7fbce7a308 100644 --- a/include/linux/mfd/twl6040.h +++ b/include/linux/mfd/twl6040.h @@ -125,8 +125,15 @@ #define TWL6040_HSDACENA (1 << 0) #define TWL6040_HSDACMODE (1 << 1) +#define TWL6040_HSDRVENA (1 << 2) #define TWL6040_HSDRVMODE (1 << 3) +/* HFLCTL/R (0x14/0x16) fields */ + +#define TWL6040_HFDACENA (1 << 0) +#define TWL6040_HFPGAENA (1 << 1) +#define TWL6040_HFDRVENA (1 << 4) + /* VIBCTLL/R (0x18/0x1A) fields */ #define TWL6040_VIBENA (1 << 0) |