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| author | Tomeu Vizoso <tomeu.vizoso@collabora.com> | 2015-03-12 15:47:54 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2015-05-04 14:21:20 +0200 |
| commit | 405990c7e834913554482538321f16f457dda50e (patch) | |
| tree | 18e44aadea2d0c8d28f7148cb647d30ea3c9f127 /Documentation/devicetree/bindings/misc | |
| parent | b787f68c36d49bb1d9236f403813641efa74a031 (diff) | |
| download | linux-405990c7e834913554482538321f16f457dda50e.tar.gz linux-405990c7e834913554482538321f16f457dda50e.tar.bz2 linux-405990c7e834913554482538321f16f457dda50e.zip | |
of: Document long-ram-code property in nvidia,tegra20-apbmisc
Needed to properly decode the RAM code register.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'Documentation/devicetree/bindings/misc')
| -rw-r--r-- | Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt index 47b205cc9cc7..4556359c5876 100644 --- a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt @@ -10,3 +10,5 @@ Required properties: The second entry gives the physical address and length of the registers indicating the strapping options. +Optional properties: +- nvidia,long-ram-code: If present, the RAM code is long (4 bit). If not, short (2 bit). |