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| author | Zhen Lei <thunder.leizhen@huawei.com> | 2020-09-29 22:14:48 +0800 |
|---|---|---|
| committer | Rob Herring <robh@kernel.org> | 2020-10-01 07:24:48 -0500 |
| commit | 5b6b3e21ec4a554583a018c46d06a75d8d460bd2 (patch) | |
| tree | 619304186a6d90cddcf3569e56324011f85cc3ae /Documentation/devicetree | |
| parent | f1d60fbb491194019c1ac4a5ea2b6f4e420614fc (diff) | |
| download | linux-5b6b3e21ec4a554583a018c46d06a75d8d460bd2.tar.gz linux-5b6b3e21ec4a554583a018c46d06a75d8d460bd2.tar.bz2 linux-5b6b3e21ec4a554583a018c46d06a75d8d460bd2.zip | |
dt-bindings: arm: hisilicon: convert hisilicon,cpuctrl bindings to json-schema
Convert the Hisilicon CPU controller binding to DT schema format using
json-schema.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Link: https://lore.kernel.org/r/20200929141454.2312-12-thunder.leizhen@huawei.com
Signed-off-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree')
| -rw-r--r-- | Documentation/devicetree/bindings/arm/hisilicon/controller/cpuctrl.yaml | 29 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt | 8 |
2 files changed, 29 insertions, 8 deletions
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/cpuctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/cpuctrl.yaml new file mode 100644 index 000000000000..f6a314db3a59 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/cpuctrl.yaml @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/cpuctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon CPU controller + +maintainers: + - Wei Xu <xuwei5@hisilicon.com> + +description: | + The clock registers and power registers of secondary cores are defined + in CPU controller, especially in HIX5HD2 SoC. + +properties: + compatible: + items: + - const: hisilicon,cpuctrl + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false +... diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt deleted file mode 100644 index ceffac537671..000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt +++ /dev/null @@ -1,8 +0,0 @@ -Hisilicon CPU controller - -Required properties: -- compatible : "hisilicon,cpuctrl" -- reg : Register address and size - -The clock registers and power registers of secondary cores are defined -in CPU controller, especially in HIX5HD2 SoC. |