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authorConor Dooley <conor.dooley@microchip.com>2023-01-04 18:05:13 +0000
committerPalmer Dabbelt <palmer@rivosinc.com>2023-02-14 19:24:05 -0800
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parentc1d6105869464635d8a2bcf87a43c05f4c0cfca4 (diff)
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dt-bindings: arm: move cpu-capacity to a shared loation
RISC-V uses the same generic topology code as arm64 & while there currently exists no binding for cpu-capacity on RISC-V, the code paths can be hit if the property is present. Move the documentation of cpu-capacity to a shared location, ahead of defining a binding for capacity-dmips-mhz on RISC-V. Update some references to this document in the process. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Yanteng Si <siyanteng@loongson.cn> Link: https://lore.kernel.org/r/20230104180513.1379453-2-conor@kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'Documentation/scheduler')
-rw-r--r--Documentation/scheduler/sched-capacity.rst2
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/scheduler/sched-capacity.rst b/Documentation/scheduler/sched-capacity.rst
index 805f85f330b5..8e2b8538bc2b 100644
--- a/Documentation/scheduler/sched-capacity.rst
+++ b/Documentation/scheduler/sched-capacity.rst
@@ -260,7 +260,7 @@ for that purpose.
The arm and arm64 architectures directly map this to the arch_topology driver
CPU scaling data, which is derived from the capacity-dmips-mhz CPU binding; see
-Documentation/devicetree/bindings/arm/cpu-capacity.txt.
+Documentation/devicetree/bindings/cpu/cpu-capacity.txt.
3.2 Frequency invariance
------------------------