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| author | Sylwester Nawrocki <s.nawrocki@samsung.com> | 2013-04-08 15:24:47 +0900 |
|---|---|---|
| committer | Kukjin Kim <kgene.kim@samsung.com> | 2013-04-08 23:43:54 +0900 |
| commit | cdbf618ab8a326cb3bdc65e8adb74bac9c347e64 (patch) | |
| tree | 36eb7164c6746ec817b77927d27d0851c73ebbac /Documentation | |
| parent | 6cec90826e9a3e505c9df91a62de59078f521dd3 (diff) | |
| download | linux-cdbf618ab8a326cb3bdc65e8adb74bac9c347e64.tar.gz linux-cdbf618ab8a326cb3bdc65e8adb74bac9c347e64.tar.bz2 linux-cdbf618ab8a326cb3bdc65e8adb74bac9c347e64.zip | |
clk: exynos4: export clocks required for fimc-is
This patch adds clock indexes for ACLK_DIV0, ACLK_DIV1,
ACLK_400_MCUISP, ACLK_MCUISP_DIV0, ACLK_MCUISP_DIV1,
DIVACLK_400_MCUISP and DIVACLK_200 so these clocks are
available to the consumers (Exynos4x12 FIMC-IS subsystem).
While at it, indentation of the mux clocks table is
corrected.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/clock/exynos4-clock.txt | 42 |
1 files changed, 28 insertions, 14 deletions
diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt index 662007e059dc..ea5e26f16aec 100644 --- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt @@ -236,22 +236,36 @@ Exynos4 SoC and this is specified where applicable. spi1_isp_sclk 381 Exynos4x12 uart_isp_sclk 382 Exynos4x12 - [Mux Clocks] + [Mux Clocks] - Clock ID SoC (if specific) - ----------------------------------------------- + Clock ID SoC (if specific) + ----------------------------------------------- + + mout_fimc0 384 + mout_fimc1 385 + mout_fimc2 386 + mout_fimc3 387 + mout_cam0 388 + mout_cam1 389 + mout_csis0 390 + mout_csis1 391 + mout_g3d0 392 + mout_g3d1 393 + mout_g3d 394 + aclk400_mcuisp 395 Exynos4x12 + + [Div Clocks] + + Clock ID SoC (if specific) + ----------------------------------------------- + + div_isp0 450 Exynos4x12 + div_isp1 451 Exynos4x12 + div_mcuisp0 452 Exynos4x12 + div_mcuisp1 453 Exynos4x12 + div_aclk200 454 Exynos4x12 + div_aclk400_mcuisp 455 Exynos4x12 - mout_fimc0 384 - mout_fimc1 385 - mout_fimc2 386 - mout_fimc3 387 - mout_cam0 388 - mout_cam1 389 - mout_csis0 390 - mout_csis1 391 - mout_g3d0 392 - mout_g3d1 393 - mout_g3d 394 Example 1: An example of a clock controller node is listed below. |