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| author | Lennert Buytenhek <buytenh@wantstofly.org> | 2006-12-03 18:51:14 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-12-03 17:52:22 +0000 |
| commit | afe4b25e7d9260d85fccb2d13c9933a987bdfc8a (patch) | |
| tree | 9b603e52ef91531089b45e5860e89d91d2e01565 /arch/arm/Kconfig | |
| parent | f5236225a3858b505221a59233af1f1158be9139 (diff) | |
| download | linux-afe4b25e7d9260d85fccb2d13c9933a987bdfc8a.tar.gz linux-afe4b25e7d9260d85fccb2d13c9933a987bdfc8a.tar.bz2 linux-afe4b25e7d9260d85fccb2d13c9933a987bdfc8a.zip | |
[ARM] 3881/4: xscale: clean up cp0/cp1 handling
XScale cores either have a DSP coprocessor (which contains a single
40 bit accumulator register), or an iWMMXt coprocessor (which contains
eight 64 bit registers.)
Because of the small amount of state in the DSP coprocessor, access to
the DSP coprocessor (CP0) is always enabled, and DSP context switching
is done unconditionally on every task switch. Access to the iWMMXt
coprocessor (CP0/CP1) is enabled only when an iWMMXt instruction is
first issued, and iWMMXt context switching is done lazily.
CONFIG_IWMMXT is supposed to mean 'the cpu we will be running on will
have iWMMXt support', but boards are supposed to select this config
symbol by hand, and at least one pxa27x board doesn't get this right,
so on that board, proc-xscale.S will incorrectly assume that we have a
DSP coprocessor, enable CP0 on boot, and we will then only save the
first iWMMXt register (wR0) on context switches, which is Bad.
This patch redefines CONFIG_IWMMXT as 'the cpu we will be running on
might have iWMMXt support, and we will enable iWMMXt context switching
if it does.' This means that with this patch, running a CONFIG_IWMMXT=n
kernel on an iWMMXt-capable CPU will no longer potentially corrupt iWMMXt
state over context switches, and running a CONFIG_IWMMXT=y kernel on a
non-iWMMXt capable CPU will still do DSP context save/restore.
These changes should make iWMMXt work on PXA3xx, and as a side effect,
enable proper acc0 save/restore on non-iWMMXt capable xsc3 cores such
as IOP13xx and IXP23xx (which will not have CONFIG_CPU_XSCALE defined),
as well as setting and using HWCAP_IWMMXT properly.
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Acked-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/Kconfig')
| -rw-r--r-- | arch/arm/Kconfig | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ce00c570459d..7be67ef4b84f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -374,6 +374,14 @@ config PLAT_IOP source arch/arm/mm/Kconfig +config IWMMXT + bool "Enable iWMMXt support" + depends CPU_XSCALE || CPU_XSC3 + default y if PXA27x + help + Enable support for iWMMXt context switching at run time if + running on a CPU that supports it. + # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER config XSCALE_PMU bool |