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author | Linus Torvalds <torvalds@linux-foundation.org> | 2023-02-21 15:21:29 -0800 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2023-02-21 15:21:29 -0800 |
commit | b327dfe05258e09c8db6e1e091c2e6d84dd426a6 (patch) | |
tree | a3c162761bc5361ebaba7c5d9068808d8242b6c4 /arch/arm/Kconfig | |
parent | eb6d5bbea2fbfaade9e29bf5ce4abe3a8384678f (diff) | |
parent | 5eb6e280432ddc9b755193552f3a070da8d7455c (diff) | |
download | linux-b327dfe05258e09c8db6e1e091c2e6d84dd426a6.tar.gz linux-b327dfe05258e09c8db6e1e091c2e6d84dd426a6.tar.bz2 linux-b327dfe05258e09c8db6e1e091c2e6d84dd426a6.zip |
Merge tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm
Pull ARM udpates from Russell King:
- Improve Kconfig help text for Cortex A8 and Cortex A9 errata
- Kconfig spelling and grammar fixes
- Allow kernel-mode VFP/Neon in softirq context
- Use Neon in softirq context
- Implement AES-CTR/GHASH version of GCM
* tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm:
ARM: 9289/1: Allow pre-ARMv5 builds with ld.lld 16.0.0 and newer
ARM: 9288/1: Kconfigs: fix spelling & grammar
ARM: 9286/1: crypto: Implement fused AES-CTR/GHASH version of GCM
ARM: 9285/1: remove meaningless arch/arm/mach-rda/Makefile
ARM: 9283/1: permit non-nested kernel mode NEON in softirq context
ARM: 9282/1: vfp: Manipulate task VFP state with softirqs disabled
ARM: 9281/1: improve Cortex A8/A9 errata help text
Diffstat (limited to 'arch/arm/Kconfig')
-rw-r--r-- | arch/arm/Kconfig | 32 |
1 files changed, 25 insertions, 7 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9f85cc34be7d..e24a9820e12f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -344,14 +344,16 @@ comment "CPU Core family selection" config ARCH_MULTI_V4 bool "ARMv4 based platforms (FA526, StrongARM)" depends on !ARCH_MULTI_V6_V7 - depends on !LD_IS_LLD + # https://github.com/llvm/llvm-project/issues/50764 + depends on !LD_IS_LLD || LLD_VERSION >= 160000 select ARCH_MULTI_V4_V5 select CPU_FA526 if !(CPU_SA110 || CPU_SA1100) config ARCH_MULTI_V4T bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" depends on !ARCH_MULTI_V6_V7 - depends on !LD_IS_LLD + # https://github.com/llvm/llvm-project/issues/50764 + depends on !LD_IS_LLD || LLD_VERSION >= 160000 select ARCH_MULTI_V4_V5 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ @@ -656,7 +658,9 @@ config ARM_ERRATA_458693 hazard might then cause a processor deadlock. The workaround enables the L1 caching of the NEON accesses and disables the PLD instruction in the ACTLR register. Note that setting specific bits in the ACTLR - register may not be available in non-secure mode. + register may not be available in non-secure mode and thus is not + available on a multiplatform kernel. This should be applied by the + bootloader instead. config ARM_ERRATA_460075 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" @@ -669,7 +673,9 @@ config ARM_ERRATA_460075 and overwritten with stale memory contents from external memory. The workaround disables the write-allocate mode for the L2 cache via the ACTLR register. Note that setting specific bits in the ACTLR register - may not be available in non-secure mode. + may not be available in non-secure mode and thus is not available on + a multiplatform kernel. This should be applied by the bootloader + instead. config ARM_ERRATA_742230 bool "ARM errata: DMB operation may be faulty" @@ -682,7 +688,10 @@ config ARM_ERRATA_742230 ordering of the two writes. This workaround sets a specific bit in the diagnostic register of the Cortex-A9 which causes the DMB instruction to behave as a DSB, ensuring the correct behaviour of - the two writes. + the two writes. Note that setting specific bits in the diagnostics + register may not be available in non-secure mode and thus is not + available on a multiplatform kernel. This should be applied by the + bootloader instead. config ARM_ERRATA_742231 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" @@ -697,7 +706,10 @@ config ARM_ERRATA_742231 replaced from one of the CPUs at the same time as another CPU is accessing it. This workaround sets specific bits in the diagnostic register of the Cortex-A9 which reduces the linefill issuing - capabilities of the processor. + capabilities of the processor. Note that setting specific bits in the + diagnostics register may not be available in non-secure mode and thus + is not available on a multiplatform kernel. This should be applied by + the bootloader instead. config ARM_ERRATA_643719 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" @@ -734,7 +746,9 @@ config ARM_ERRATA_743622 register of the Cortex-A9 which disables the Store Buffer optimisation, preventing the defect from occurring. This has no visible impact on the overall performance or power consumption of the - processor. + processor. Note that setting specific bits in the diagnostics register + may not be available in non-secure mode and thus is not available on a + multiplatform kernel. This should be applied by the bootloader instead. config ARM_ERRATA_751472 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" @@ -746,6 +760,10 @@ config ARM_ERRATA_751472 completion of a following broadcasted operation if the second operation is received by a CPU before the ICIALLUIS has completed, potentially leading to corrupted entries in the cache or TLB. + Note that setting specific bits in the diagnostics register may + not be available in non-secure mode and thus is not available on + a multiplatform kernel. This should be applied by the bootloader + instead. config ARM_ERRATA_754322 bool "ARM errata: possible faulty MMU translations following an ASID switch" |