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author | Arnd Bergmann <arnd@arndb.de> | 2013-06-20 01:43:19 +0200 |
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committer | Arnd Bergmann <arnd@arndb.de> | 2013-06-20 01:43:19 +0200 |
commit | a44bde66bec168889c95bd1d0d15834b02387901 (patch) | |
tree | 70e8d2bbc26d72d51928e6aacb274829f835a5d1 /arch/arm/boot/dts/Makefile | |
parent | ef0a3402cccf75b43b1ed854f57fb11b54a1241a (diff) | |
parent | 50dbb4cfbc264b074759e8fb5d8e0c0496a1b072 (diff) | |
download | linux-a44bde66bec168889c95bd1d0d15834b02387901.tar.gz linux-a44bde66bec168889c95bd1d0d15834b02387901.tar.bz2 linux-a44bde66bec168889c95bd1d0d15834b02387901.zip |
Merge tag 'zynq-dt-for-3.11' of git://git.xilinx.com/linux-xlnx into next/dt
From Michal Simek:
arm: Xilinx Zynq dt changes for v3.11
The branch contains:
- DT uart handling cleanup
- Support for zc706 and zed board
- Removal of board compatible string
* tag 'zynq-dt-for-3.11' of git://git.xilinx.com/linux-xlnx:
arm: dt: zynq: Add support for the zed platform
arm: dt: zynq: Add support for the zc706 platform
arm: dt: zynq: Use 'status' property for UART nodes
arm: zynq: Remove board specific compatibility string
clk: zynq: Remove deprecated clock code
arm: zynq: Migrate platform to clock controller
clk: zynq: Add clock controller driver
clk: zynq: Factor out PLL driver
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/boot/dts/Makefile')
-rw-r--r-- | arch/arm/boot/dts/Makefile | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 4823c3121ee2..4c904a8e458a 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -216,7 +216,9 @@ dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \ wm8650-mid.dtb \ wm8750-apc8750.dtb \ wm8850-w70v2.dtb -dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb +dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \ + zynq-zc706.dtb \ + zynq-zed.dtb targets += dtbs targets += $(dtb-y) |