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authorMaxime Ripard <maxime.ripard@free-electrons.com>2015-06-17 11:44:24 +0200
committerMaxime Ripard <maxime.ripard@free-electrons.com>2015-07-28 14:41:50 +0200
commitb03e081672d9ccbff8185dd655a7bbba24223b4a (patch)
tree3b459a754c54eb959515bc173cb33cce5756c094 /arch/arm/boot/dts/sun5i-a13-utoo-p66.dts
parent79ae3e66f8d7ba51c02773897a8f1a37b496d9a3 (diff)
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ARM: sunxi: dt: Convert users to the PIO interrupts binding
The current DTs were setting the cell size to 2, but used the default xlate function that was assuming an interrupt cell size of 1, leading to the second part of the cell (the flags) being ignored, while we were having an inconsistent binding between the interrupts and gpio (that could also be used as interrupts). That "binding" doesn't work either with newer SoCs that have multiple irq banks. Now that we fixed the pinctrl driver to handle this like it should always have been handled, convert the DT users, and while we're at it, remove the size-cells property of PIO that is completely useless. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/sun5i-a13-utoo-p66.dts')
-rw-r--r--arch/arm/boot/dts/sun5i-a13-utoo-p66.dts2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts b/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts
index 3043aac2c765..eb793d5a2bd6 100644
--- a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts
+++ b/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts
@@ -93,7 +93,7 @@
compatible = "chipone,icn8318";
reg = <0x40>;
interrupt-parent = <&pio>;
- interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* EINT9 (PG9) */
+ interrupts = <6 9 IRQ_TYPE_EDGE_FALLING>; /* EINT9 (PG9) */
pinctrl-names = "default";
pinctrl-0 = <&ts_wake_pin_p66>;
wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */