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author | Tony Lindgren <tony@atomide.com> | 2021-01-15 12:48:43 +0200 |
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committer | Tony Lindgren <tony@atomide.com> | 2021-01-15 12:48:43 +0200 |
commit | 715a1284d89a740b197b3bad5eb20d36a397382f (patch) | |
tree | 07ad2960ab66e56b3d1e151036262019a18e3df1 /arch/arm/boot/dts/tegra20.dtsi | |
parent | 181739822cf6f8f4e12b173913af2967a28906c0 (diff) | |
parent | 06862d789ddde8a99c1e579e934ca17c15a84755 (diff) | |
download | linux-715a1284d89a740b197b3bad5eb20d36a397382f.tar.gz linux-715a1284d89a740b197b3bad5eb20d36a397382f.tar.bz2 linux-715a1284d89a740b197b3bad5eb20d36a397382f.zip |
Merge branch 'cpuidle-fix' into fixes
Diffstat (limited to 'arch/arm/boot/dts/tegra20.dtsi')
-rw-r--r-- | arch/arm/boot/dts/tegra20.dtsi | 33 |
1 files changed, 31 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 72a4211a618f..6ce498178105 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -6,6 +6,8 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/soc/tegra-pmc.h> +#include "tegra20-peripherals-opp.dtsi" + / { compatible = "nvidia,tegra20"; interrupt-parent = <&lic>; @@ -111,6 +113,17 @@ nvidia,head = <0>; + interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>, + <&mc TEGRA20_MC_DISPLAY0B &emc>, + <&mc TEGRA20_MC_DISPLAY1B &emc>, + <&mc TEGRA20_MC_DISPLAY0C &emc>, + <&mc TEGRA20_MC_DISPLAYHC &emc>; + interconnect-names = "wina", + "winb", + "winb-vfilter", + "winc", + "cursor"; + rgb { status = "disabled"; }; @@ -128,6 +141,17 @@ nvidia,head = <1>; + interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>, + <&mc TEGRA20_MC_DISPLAY0BB &emc>, + <&mc TEGRA20_MC_DISPLAY1BB &emc>, + <&mc TEGRA20_MC_DISPLAY0CB &emc>, + <&mc TEGRA20_MC_DISPLAYHCB &emc>; + interconnect-names = "wina", + "winb", + "winb-vfilter", + "winc", + "cursor"; + rgb { status = "disabled"; }; @@ -630,15 +654,20 @@ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; #reset-cells = <1>; #iommu-cells = <0>; + #interconnect-cells = <1>; }; - memory-controller@7000f400 { + emc: memory-controller@7000f400 { compatible = "nvidia,tegra20-emc"; - reg = <0x7000f400 0x200>; + reg = <0x7000f400 0x400>; interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_EMC>; #address-cells = <1>; #size-cells = <0>; + #interconnect-cells = <0>; + + operating-points-v2 = <&emc_icc_dvfs_opp_table>; + nvidia,memory-controller = <&mc>; }; fuse@7000f800 { |