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author | Stephen Warren <swarren@nvidia.com> | 2013-03-27 16:53:20 -0600 |
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committer | Stephen Warren <swarren@nvidia.com> | 2013-06-12 14:56:40 -0600 |
commit | 23037bbd9661b53236ebe934c77952e8f73f1c7a (patch) | |
tree | 27136980501642eea2e20ae54e403750015df30e /arch/arm/boot/dts/tegra30-beaver.dts | |
parent | aa5ae424952fe2d1c2ca2340a433c3e3407262f7 (diff) | |
download | linux-23037bbd9661b53236ebe934c77952e8f73f1c7a.tar.gz linux-23037bbd9661b53236ebe934c77952e8f73f1c7a.tar.bz2 linux-23037bbd9661b53236ebe934c77952e8f73f1c7a.zip |
ARM: tegra: enable audio on Beaver
Beaver uses the RT5640 audio CODEC. Instantiate this on the I2C bus, and
add the top-level "sound" node to hook everything together and provide a
"sound card" device.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra30-beaver.dts')
-rw-r--r-- | arch/arm/boot/dts/tegra30-beaver.dts | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index a7a34b96717c..87c5f7b7c271 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -116,6 +116,15 @@ status = "okay"; clock-frequency = <100000>; + rt5640: rt5640 { + compatible = "realtek,rt5640"; + reg = <0x1c>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(X, 3) GPIO_ACTIVE_HIGH>; + realtek,ldo1-en-gpios = + <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>; + }; + tps62361 { compatible = "ti,tps62361"; reg = <0x60>; @@ -404,4 +413,24 @@ gpios = <&gpio TEGRA_GPIO(L, 0) GPIO_ACTIVE_HIGH>; }; }; + + sound { + compatible = "nvidia,tegra-audio-rt5640-beaver", + "nvidia,tegra-audio-rt5640"; + nvidia,model = "NVIDIA Tegra Beaver"; + + nvidia,audio-routing = + "Headphones", "HPOR", + "Headphones", "HPOL"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&rt5640>; + + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; + + clocks = <&tegra_car TEGRA30_CLK_PLL_A>, + <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA30_CLK_EXTERN1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + }; }; |