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| author | Claudiu Beznea <claudiu.beznea@microchip.com> | 2021-04-15 13:50:04 +0300 |
|---|---|---|
| committer | Nicolas Ferre <nicolas.ferre@microchip.com> | 2021-07-19 14:32:12 +0200 |
| commit | 892e1f4a3ae58c1cd376d952d45dca6f20dc712c (patch) | |
| tree | f6de9f1e138eb48423937d2ceb3067d3234ad7ce /arch/arm/mach-at91/at91sam9.c | |
| parent | 2c26cb4d6944edf0a65a4b1fdeacdcc816261739 (diff) | |
| download | linux-892e1f4a3ae58c1cd376d952d45dca6f20dc712c.tar.gz linux-892e1f4a3ae58c1cd376d952d45dca6f20dc712c.tar.bz2 linux-892e1f4a3ae58c1cd376d952d45dca6f20dc712c.zip | |
ARM: at91: pm: add sama7g5 ddr phy controller
SAMA7G5 self-refresh procedure accesses also the DDR PHY registers.
Adapt the code so that the at91_dt_ramc() to look also for DDR PHYs,
in case it is mandatory.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20210415105010.569620-19-claudiu.beznea@microchip.com
Diffstat (limited to 'arch/arm/mach-at91/at91sam9.c')
0 files changed, 0 insertions, 0 deletions