summaryrefslogtreecommitdiffstats
path: root/arch/arm/mm/Kconfig
diff options
context:
space:
mode:
authorMarek Szyprowski <m.szyprowski@samsung.com>2019-05-28 09:38:14 +0100
committerRussell King <rmk+kernel@armlinux.org.uk>2019-06-20 22:29:58 +0100
commit5f41f9198f296091c6a58bc2e86af1e9f019b2a3 (patch)
treef309f6b56520b0b974c46cff4de32b3d8decc1c1 /arch/arm/mm/Kconfig
parent304009a182b9fc6eff74060b415c8240380501cb (diff)
downloadlinux-5f41f9198f296091c6a58bc2e86af1e9f019b2a3.tar.gz
linux-5f41f9198f296091c6a58bc2e86af1e9f019b2a3.tar.bz2
linux-5f41f9198f296091c6a58bc2e86af1e9f019b2a3.zip
ARM: 8864/1: Add workaround for I-Cache line size mismatch between CPU cores
Some big.LITTLE systems have I-Cache line size mismatch between LITTLE and big cores. This patch adds a workaround for proper I-Cache support on such systems. Without it, some class of the userspace code (typically self-modifying) might suffer from random SIGILL failures. Similar workaround already exists for ARM64 architecture. I has been added by commit 116c81f427ff ("arm64: Work around systems with mismatched cache line sizes"). Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'arch/arm/mm/Kconfig')
-rw-r--r--arch/arm/mm/Kconfig8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index b169e580bf82..cc798115aa9b 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -780,6 +780,14 @@ config CPU_ICACHE_DISABLE
Say Y here to disable the processor instruction cache. Unless
you have a reason not to or are unsure, say N.
+config CPU_ICACHE_MISMATCH_WORKAROUND
+ bool "Workaround for I-Cache line size mismatch between CPU cores"
+ depends on SMP && CPU_V7
+ help
+ Some big.LITTLE systems have I-Cache line size mismatch between
+ LITTLE and big cores. Say Y here to enable a workaround for
+ proper I-Cache support on such systems. If unsure, say N.
+
config CPU_DCACHE_DISABLE
bool "Disable D-Cache (C-bit)"
depends on (CPU_CP15 && !SMP) || CPU_V7M