Merge tag 'arm-dt-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC devicetree updates from Arnd Bergmann:
 "After the last release contained a surprising amount of new 32-bit
  machines, this time two thirds of the code changes are for 64-bit.

  The usual updates to existing files include:

   - Device tree compiler warning fixes for Berlin, Renesas, SoCFPGA,
     nomadik, stm32, Allwinner, TI Keystone

   - Support for additional devices on existing machines on Renesas,
     SoCFPGA, at91, hisilicon, OMAP, Tegra, TI K3, Allwinner, Broadcom,
     ux500, Mediatek, Marvell Armada, Marvell MMP, ZynqMP, AMLogic,
     Qualcomm, i.MX, Layerscape, Actions, ASpeed, Toshiba

   - Cleanups and minor fixes for Renesas, at91, mstar, ux500, Samsung,
     stm32, Tegra, Broadcom, Mediatek, Marvell MMP, AMLogic, Qualcomm,
     i.MX, Rockchip, ASpeed, Zynq

  Only three new SoCs this time, but a number of boards across:

  Renesas:
   - Two Beacon EmbeddedWorks boards (RZ/G2H and RZ/G2N based)

  Intel SoCFPGA:
   - eASIC N5X board (N5X)

  ST-Ericsson Ux500:
   - Samsung GT-I9070 (Janice) phone (u8500)

  TI OMAP:
   - MYIR Tech Limited development board (AM335X)

  Allwinner/sunxi:
   - SL631 Action Camera (V3)
   - PineTab Early Adopter tablet (A64)

  Broadcom:
   - BCM4906 networking chip
   - Netgear R8000P router (BCM4906)

  AMLogic:
   - Hardkernel ODROID-HC4 development board (SM1)
   - Beelink GS-King-X TV Box (S922X)

  Qualcomm:
   - Snapdragon 888 / SM8350 high-end phone SoC
   - Qualcomm SDX55 5G modem as standalone SoC
   - Snapdragon MTP reference board (SM8350)
   - Snapdragon MTP reference board (SDX55)
   - Sony Kitakami phones: Xperia Z3+/Z4/Z5 (APQ8094)
   - Alcatel Idol 3 phone (MSM8916)
   - ASUS Zenfone 2 Laser phone (MSM8916)
   - BQ Aquaris X5 aka Longcheer L8910 phone (MSM8916)
   - OnePlus6 phone (SDM845)
   - OnePlus6T phone (SDM845)
   - Alfa Network AP120C-AC access point (IPQ4018)

  NXP i.MX6 (32-bit):
   - Plymovent BAS base system controller for filter systems (imx6dl)
   - Protonic MVT industrial touchscreen terminals (imx6dl)
   - Protonic PRTI6G reference board (imx6ul)
   - Kverneland UT1, UT1Q, UT1P, TGO agricultural terminals (imx6q/dl/qp)

  NXP i.MX8 (64-bit)
   - Beacon i.MX8M Nano development kit (imx8mn)
   - Boundary Devices i.MX8MM Nitrogen SBC (imx8mm)
   - Gateworks Venice i.MX 8M Mini Development Kits (imx8mm)
   - phyBOARD-Pollux-i.MX8MP (imx8mp)
   - Purism Librem5 Evergreen phone (imx8mp)
   - Kontron SMARC-sAL28 system-on-module(imx8mp)

  Rockchip:
   - NanoPi M4B Single-board computer (RK3399)
   - Radxa Rock Pi E router SBC (RK3328)

  ASpeed:
   - Ampere Mt. Jade, a BMC for an x86 server (AST2500)
   - IBM Everest, a BMC for a Power10 server (AST2600)
   - Supermicro x11spi, a BMC for an ARM server (AST2500)

  Zynq:
   - Ebang EBAZ4205, FPGA board (Zynq-7000)
   - ZynqMP zcu104 revC reference platform (ZynqMP)"

* tag 'arm-dt-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (584 commits)
  ARM: dts: aspeed: align GPIO hog names with dtschema
  ARM: dts: aspeed: fix PCA95xx GPIO expander properties on Portwell
  dt-bindings: spi: zynq: Convert Zynq QSPI binding to yaml
  arm: dts: visconti: Add DT support for Toshiba Visconti5 GPIO driver
  ARM: dts: aspeed: ast2600evb: Add enable ehci and uhci
  ARM: dts: aspeed: mowgli: Add i2c rtc device
  ARM: dts: aspeed: amd-ethanolx: Enable secondary LPC snooping address
  dt-bindings: arm: xilinx: Add missing Zturn boards
  ARM: dts: ebaz4205: add pinctrl entries for switches
  ARM: dts: add Ebang EBAZ4205 device tree
  dt-bindings: arm: add Ebang EBAZ4205 board
  dt-bindings: add ebang vendor prefix
  ARM: dts: aspeed: Add Everest BMC machine
  ARM: dts: aspeed: inspur-fp5280g2: Add ipsps1 driver
  ARM: dts: aspeed: inspur-fp5280g2: Add GPIO line names
  ARM: dts: aspeed: Add Supermicro x11spi BMC machine
  ARM: dts: aspeed: g220a: Fix some gpio
  ARM: dts: aspeed: g220a: Enable ipmb
  ARM: dts: aspeed: rainier: Add eMMC clock phase compensation
  ARM: dts: aspeed: Add LCLK to lpc-snoop
  ...

1 files changed, 186 insertions, 0 deletions

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
new file mode 100644
index 000000000000..905b68a3daa5
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2020 Gateworks Corporation
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	aliases {
+		usb0 = &usbotg1;
+		usb1 = &usbotg2;
+	};
+
+	led-controller {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_leds>;
+
+		led-0 {
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+			linux,default-trigger = "heartbeat";
+		};
+
+		led-1 {
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
+			gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+	};
+
+	pps {
+		compatible = "pps-gpio";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_pps>;
+		gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+	};
+
+	reg_usb_otg1_vbus: regulator-usb-otg1 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_reg_usb1_en>;
+		compatible = "regulator-fixed";
+		regulator-name = "usb_otg1_vbus";
+		gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+};
+
+/* off-board header */
+&ecspi2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_spi2>;
+	cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&i2c2 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+
+	accelerometer@19 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_accel>;
+		compatible = "st,lis2de12";
+		reg = <0x19>;
+		st,drdy-int-pin = <1>;
+		interrupt-parent = <&gpio4>;
+		interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-names = "INT1";
+	};
+};
+
+/* off-board header */
+&i2c3 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	status = "okay";
+};
+
+/* GPS */
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+/* off-board header */
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3>;
+	status = "okay";
+};
+
+&usbotg1 {
+	dr_mode = "otg";
+	vbus-supply = <&reg_usb_otg1_vbus>;
+	status = "okay";
+};
+
+&usbotg2 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	pinctrl_hog: hoggrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3		0x40000041 /* PLUG_TEST */
+			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6	0x40000041 /* PCI_USBSEL */
+			MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7	0x40000041 /* PCIE_WDIS# */
+			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7	0x40000041 /* DIO0 */
+			MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9	0x40000041 /* DIO1 */
+			MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3	0x40000041 /* DIO2 */
+			MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4	0x40000041 /* DIO2 */
+		>;
+	};
+
+	pinctrl_accel: accelgrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5	0x159
+		>;
+	};
+
+	pinctrl_gpio_leds: gpioledgrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5	0x19
+			MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4		0x19
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3
+			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
+		>;
+	};
+
+	pinctrl_pps: ppsgrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x41
+		>;
+	};
+
+	pinctrl_reg_usb1_en: regusb1grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x41
+			MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC	0x41
+		>;
+	};
+
+	pinctrl_spi2: spi2grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0xd6
+			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0xd6
+			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0xd6
+			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0xd6
+		>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140
+			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140
+		>;
+	};
+
+	pinctrl_uart3: uart3grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX	0x140
+			MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX	0x140
+		>;
+	};
+};