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| author | Rafał Miłecki <rafal@milecki.pl> | 2024-06-05 10:54:33 +0200 |
|---|---|---|
| committer | AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2024-10-16 12:06:03 +0200 |
| commit | 21e28a0722e4b0b8851d6d16da57309adfaf0e6b (patch) | |
| tree | 6639b124222900e23bd7aec625b2f9b01070ad9b /arch/arm64/boot/dts/mediatek | |
| parent | 0fd4ffc8709e08179cd25bf71fa4852b2e81671b (diff) | |
| download | linux-21e28a0722e4b0b8851d6d16da57309adfaf0e6b.tar.gz linux-21e28a0722e4b0b8851d6d16da57309adfaf0e6b.tar.bz2 linux-21e28a0722e4b0b8851d6d16da57309adfaf0e6b.zip | |
arm64: dts: mediatek: mt7988: add UART controllers
MT7988 has three on-SoC UART controllers that support M16C450 and
M16550A modes.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20240605085433.26513-2-zajec5@gmail.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Diffstat (limited to 'arch/arm64/boot/dts/mediatek')
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 35 |
1 files changed, 34 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index aa728331e876..7690a83911af 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -86,7 +86,7 @@ #clock-cells = <1>; }; - clock-controller@1001b000 { + topckgen: clock-controller@1001b000 { compatible = "mediatek,mt7988-topckgen", "syscon"; reg = <0 0x1001b000 0 0x1000>; #clock-cells = <1>; @@ -124,6 +124,39 @@ status = "disabled"; }; + serial@11000000 { + compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; + reg = <0 0x11000000 0 0x100>; + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uart", "wakeup"; + clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_52M_UART0_CK>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + serial@11000100 { + compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; + reg = <0 0x11000100 0 0x100>; + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uart", "wakeup"; + clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_52M_UART1_CK>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + serial@11000200 { + compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; + reg = <0 0x11000200 0 0x100>; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uart", "wakeup"; + clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_52M_UART2_CK>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + i2c@11003000 { compatible = "mediatek,mt7981-i2c"; reg = <0 0x11003000 0 0x1000>, |