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| author | Fei Shao <fshao@chromium.org> | 2024-10-14 19:09:31 +0800 |
|---|---|---|
| committer | AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2024-10-16 12:06:06 +0200 |
| commit | d279c73576a7ce87f2f7ba510311c3c53ded11ea (patch) | |
| tree | 4e87e96443af3ca4f7e73757dfe73a999416aba2 /arch/arm64/boot/dts/mediatek | |
| parent | 26132136eb27c6e4960612be51b7a56c9d3b3e53 (diff) | |
| download | linux-d279c73576a7ce87f2f7ba510311c3c53ded11ea.tar.gz linux-d279c73576a7ce87f2f7ba510311c3c53ded11ea.tar.bz2 linux-d279c73576a7ce87f2f7ba510311c3c53ded11ea.zip | |
arm64: dts: mediatek: mt8188: Add eDP and DP TX nodes
Add edp-tx and dp-tx nodes for the Embedded DisplayPort (eDP) and
DisplayPort ports to connect to DP-INTF ports and panels, and add the
efuse cell for the DP calibration data.
Individual board device tree should enable the nodes and connect input
and output ports as needed.
Signed-off-by: Fei Shao <fshao@chromium.org>
Link: https://lore.kernel.org/r/20241014111053.2294519-10-fshao@chromium.org
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Diffstat (limited to 'arch/arm64/boot/dts/mediatek')
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8188.dtsi | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index 0935f2ccb2b0..2710e18ce696 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -2021,6 +2021,10 @@ #address-cells = <1>; #size-cells = <1>; + dp_calib_data: dp-calib@1a0 { + reg = <0x1a0 0xc>; + }; + lvts_efuse_data1: lvts1-calib@1ac { reg = <0x1ac 0x40>; }; @@ -2882,5 +2886,27 @@ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x4000 0x1000>; }; + + edp_tx: edp-tx@1c500000 { + compatible = "mediatek,mt8188-edp-tx"; + reg = <0 0x1c500000 0 0x8000>; + interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>; + nvmem-cells = <&dp_calib_data>; + nvmem-cell-names = "dp_calibration_data"; + power-domains = <&spm MT8188_POWER_DOMAIN_EDP_TX>; + max-linkrate-mhz = <8100>; + status = "disabled"; + }; + + dp_tx: dp-tx@1c600000 { + compatible = "mediatek,mt8188-dp-tx"; + reg = <0 0x1c600000 0 0x8000>; + interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>; + nvmem-cells = <&dp_calib_data>; + nvmem-cell-names = "dp_calibration_data"; + power-domains = <&spm MT8188_POWER_DOMAIN_DP_TX>; + max-linkrate-mhz = <5400>; + status = "disabled"; + }; }; }; |