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| author | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2023-10-12 22:51:28 +0530 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2023-12-02 17:21:58 -0800 |
| commit | ec987b5efd59fdea4178d824d8ec4bbdf3019bdf (patch) | |
| tree | f0505ea54546ff384617f8cab45e75d9e3d2a048 /arch/arm64/boot/dts/qcom/sdm845.dtsi | |
| parent | 14259fcdaf72d3ce93ad9c2b12cc0e96ed5a0c4e (diff) | |
| download | linux-ec987b5efd59fdea4178d824d8ec4bbdf3019bdf.tar.gz linux-ec987b5efd59fdea4178d824d8ec4bbdf3019bdf.tar.bz2 linux-ec987b5efd59fdea4178d824d8ec4bbdf3019bdf.zip | |
arm64: dts: qcom: sdm845: Add OPP table support to UFSHC
UFS host controller, when scaling gears, should choose appropriate
performance state of RPMh power domain controller along with clock
frequency. So let's add the OPP table support to specify both clock
frequency and RPMh performance states replacing the old "freq-table-hz"
property.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
[mani: Splitted pd change and used rpmhpd_opp_low_svs]
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20231012172129.65172-5-manivannan.sadhasivam@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/qcom/sdm845.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sdm845.dtsi | 42 |
1 files changed, 32 insertions, 10 deletions
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 22cf162dd816..9b62ca0229bd 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2595,22 +2595,44 @@ <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; - freq-table-hz = - <50000000 200000000>, - <0 0>, - <0 0>, - <37500000 150000000>, - <0 0>, - <0 0>, - <0 0>, - <0 0>, - <75000000 300000000>; + + operating-points-v2 = <&ufs_opp_table>; interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mem_noc SLAVE_EBI1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; interconnect-names = "ufs-ddr", "cpu-ufs"; status = "disabled"; + + ufs_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <37500000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <150000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; }; ufs_mem_phy: phy@1d87000 { |