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| author | Lokesh Vutla <lokeshvutla@ti.com> | 2019-06-14 20:20:00 +0530 |
|---|---|---|
| committer | Tero Kristo <t-kristo@ti.com> | 2019-06-19 11:59:49 +0300 |
| commit | 073086fc68d7f6a8bb473fd74a47c7254cf95de8 (patch) | |
| tree | 235a6a331310b910dd2617a10ff9e9d0c28a0a3f /arch/arm64/boot/dts/ti | |
| parent | 1463a70dfc871ab5a9353b6d9c34f9b770f12650 (diff) | |
| download | linux-073086fc68d7f6a8bb473fd74a47c7254cf95de8.tar.gz linux-073086fc68d7f6a8bb473fd74a47c7254cf95de8.tar.bz2 linux-073086fc68d7f6a8bb473fd74a47c7254cf95de8.zip | |
arm64: dts: ti: k3-j721e: Add interrupt controllers in main domain
Main domain in J721E has the following interrupt controller instances:
- Main Domain GPIO Interrupt router connected to gpio in main domain.
- Under the Main Domain Navigator Subsystem(NAVSS)
- Main Navss Interrupt Router connected to main navss inta and mailboxes.
- Main Navss Interrupt Aggregator connected to main domain UDMASS
Add DT nodes for the interrupt controllers available in main domain.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Diffstat (limited to 'arch/arm64/boot/dts/ti')
| -rw-r--r-- | arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 36c51ff9a898..a01308142f77 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -50,6 +50,17 @@ #iommu-cells = <1>; }; + main_gpio_intr: interrupt-controller0 { + compatible = "ti,sci-intr"; + ti,intr-trigger-type = <1>; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <2>; + ti,sci = <&dmsc>; + ti,sci-dst-id = <14>; + ti,sci-rm-range-girq = <0x1>; + }; + cbass_main_navss: interconnect0 { compatible = "simple-bus"; #address-cells = <2>; @@ -66,6 +77,18 @@ ti,sci-dst-id = <14>; ti,sci-rm-range-girq = <0>, <2>; }; + + main_udmass_inta: interrupt-controller@33d00000 { + compatible = "ti,sci-inta"; + reg = <0x0 0x33d00000 0x0 0x100000>; + interrupt-controller; + interrupt-parent = <&main_navss_intr>; + msi-controller; + ti,sci = <&dmsc>; + ti,sci-dev-id = <209>; + ti,sci-rm-range-vint = <0xa>; + ti,sci-rm-range-global-event = <0xd>; + }; }; secure_proxy_main: mailbox@32c00000 { |