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author | Linus Torvalds <torvalds@linux-foundation.org> | 2016-03-16 08:36:55 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2016-03-16 08:36:55 -0700 |
commit | 047486d8e7c2a7e8d75b068b69cb67b47364f5d4 (patch) | |
tree | 8c9b5f7a68128f9b9a695717e662918c1683996c /arch/arm64/boot | |
parent | 9256d5a308c95a50c6e85d682492ae1f86a70f9b (diff) | |
parent | 7cc5a5d3cd4cca0a3852d1500e8c50fe191bcc9d (diff) | |
download | linux-047486d8e7c2a7e8d75b068b69cb67b47364f5d4.tar.gz linux-047486d8e7c2a7e8d75b068b69cb67b47364f5d4.tar.bz2 linux-047486d8e7c2a7e8d75b068b69cb67b47364f5d4.zip |
Merge tag 'edac_for_4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp
Pull EDAC updates from Borislav Petkov:
- Altera: L2 cache and On-Chip RAM support (Thor Thayer).
- EDAC: Workqueue handling cleanups (Borislav Petkov).
- Xgene: Register bus error handling (Loc Ho).
- Misc small fixes.
* tag 'edac_for_4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp:
ARM: socfpga: Enable OCRAM ECC on startup
ARM: socfpga: Enable L2 cache ECC on startup
ARM: dts: Add Altera L2 Cache and OCRAM EDAC entries
EDAC, altera: Add Altera L2 cache and OCRAM support
EDAC: Use edac_debugfs_remove_recursive() in edac_debugfs_exit()
EDAC, mpc85xx: Silence unused variable warning
EDAC: Cleanup/sync workqueue functions
EDAC: Kill workqueue setup/teardown functions
EDAC: Balance workqueue setup and teardown
arm64: Update the APM X-Gene EDAC node with the RB register resource
EDAC, xgene: Add missing SoC register bus error handling
Documentation, EDAC: Update xgene binding for missing register bus
EDAC, amd64_edac: Shift wrapping issue in f1x_get_norm_dct_addr()
Diffstat (limited to 'arch/arm64/boot')
-rw-r--r-- | arch/arm64/boot/dts/apm/apm-storm.dtsi | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index fe30f7671ea3..3e40bd469cea 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -493,6 +493,11 @@ reg = <0x0 0x1054a000 0x0 0x20>; }; + rb: rb@7e000000 { + compatible = "apm,xgene-rb", "syscon"; + reg = <0x0 0x7e000000 0x0 0x10>; + }; + edac@78800000 { compatible = "apm,xgene-edac"; #address-cells = <2>; @@ -502,6 +507,7 @@ regmap-mcba = <&mcba>; regmap-mcbb = <&mcbb>; regmap-efuse = <&efuse>; + regmap-rb = <&rb>; reg = <0x0 0x78800000 0x0 0x100>; interrupts = <0x0 0x20 0x4>, <0x0 0x21 0x4>, |