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authorDuc Dang <dhdang@apm.com>2015-12-29 17:05:31 -0800
committerDuc Dang <dhdang@apm.com>2015-12-29 17:05:31 -0800
commit9ebf47bb748c17ebb2f9dde9169ed7a7612c3137 (patch)
treea029845c81e14e21953b75908008e40fab5a419c /arch/arm64/boot
parent0fe8588fcaac6fff08937a338feb8e3082fe9e57 (diff)
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arm64: dts: X-Gene v2: I2C1 clock is always on
X-Gene v2 I2C0 and I2C1 controllers share the same clock enable register field. This patch remove clock node for I2C1 and leave I2C1 clock always on as having it toggled on/off will affect I2C0 operation. Signed-off-by: Duc Dang <dhdang@apm.com>
Diffstat (limited to 'arch/arm64/boot')
-rw-r--r--arch/arm64/boot/dts/apm/apm-shadowcat.dtsi15
1 files changed, 1 insertions, 14 deletions
diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
index 4b3837bda5a6..5d87a3dc44b8 100644
--- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
@@ -334,19 +334,6 @@
clock-output-names = "rngpkaclk";
};
- i2c1clk: i2c1clk@17000000 {
- compatible = "apm,xgene-device-clock";
- #clock-cells = <1>;
- clocks = <&sbapbclk 0>;
- reg = <0x0 0x17000000 0x0 0x2000>;
- reg-names = "csr-reg";
- csr-offset = <0xc>;
- csr-mask = <0x4>;
- enable-offset = <0x10>;
- enable-mask = <0x4>;
- clock-output-names = "i2c1clk";
- };
-
i2c4clk: i2c4clk@1704c000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
@@ -656,7 +643,7 @@
reg = <0x0 0x10511000 0x0 0x1000>;
interrupts = <0 0x45 0x4>;
#clock-cells = <1>;
- clocks = <&i2c1clk 0>;
+ clocks = <&sbapbclk 0>;
bus_num = <1>;
};