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| author | Catalin Marinas <catalin.marinas@arm.com> | 2012-03-05 11:49:28 +0000 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2012-09-17 13:42:00 +0100 |
| commit | f1a0c4aa0937975b53991842a494f741d7769b02 (patch) | |
| tree | 9b344c5267cb982b14a2372a0a20714f5b36d61a /arch/arm64/include/asm/tlb.h | |
| parent | 9cce7a435f89c9e60f244d44da2cf1cf4ed094ac (diff) | |
| download | linux-f1a0c4aa0937975b53991842a494f741d7769b02.tar.gz linux-f1a0c4aa0937975b53991842a494f741d7769b02.tar.bz2 linux-f1a0c4aa0937975b53991842a494f741d7769b02.zip | |
arm64: Cache maintenance routines
The patch adds functionality required for cache maintenance. The AArch64
architecture mandates non-aliasing VIPT or PIPT D-cache and VIPT (may
have aliases) or ASID-tagged VIVT I-cache. Cache maintenance operations
are automatically broadcast in hardware between CPUs.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Olof Johansson <olof@lixom.net>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm64/include/asm/tlb.h')
0 files changed, 0 insertions, 0 deletions