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| author | Marc Zyngier <maz@kernel.org> | 2021-10-17 13:42:23 +0100 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2021-10-19 10:56:20 +0100 |
| commit | 9ee840a96042cef9f7d36337ce05144d6c013858 (patch) | |
| tree | 26cd3150704d6868e2bd19a493eacbfc2d0f0e11 /arch/arm64/kernel/traps.c | |
| parent | fdf865988b5a404f91f86a1b3b665440a9ebafb2 (diff) | |
| download | linux-9ee840a96042cef9f7d36337ce05144d6c013858.tar.gz linux-9ee840a96042cef9f7d36337ce05144d6c013858.tar.bz2 linux-9ee840a96042cef9f7d36337ce05144d6c013858.zip | |
arm64: Add CNT{P,V}CTSS_EL0 alternatives to cnt{p,v}ct_el0
CNTPCTSS_EL0 and CNTVCTSS_EL0 are alternatives to the usual
CNTPCT_EL0 and CNTVCT_EL0 that do not require a previous ISB
to be synchronised (SS stands for Self-Synchronising).
Use the ARM64_HAS_ECV capability to control alternative sequences
that switch to these low(er)-cost primitives. Note that the
counter access in the VDSO is for now left alone until we decide
whether we want to allow this.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211017124225.3018098-16-maz@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'arch/arm64/kernel/traps.c')
0 files changed, 0 insertions, 0 deletions