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| author | Shenming Lu <lushenming@huawei.com> | 2020-11-28 22:18:57 +0800 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2020-11-30 11:18:29 +0000 |
| commit | 57e3cebd022fbc035dcf190ac789fd2ffc747f5b (patch) | |
| tree | a566c7a05f60d395cc47e072fdd8e1d600bb535e /arch/arm64/kvm/vgic/vgic-v4.c | |
| parent | bf118a5cb7e6d17e7ec9492e4dc676e7e7b69d01 (diff) | |
| download | linux-57e3cebd022fbc035dcf190ac789fd2ffc747f5b.tar.gz linux-57e3cebd022fbc035dcf190ac789fd2ffc747f5b.tar.bz2 linux-57e3cebd022fbc035dcf190ac789fd2ffc747f5b.zip | |
KVM: arm64: Delay the polling of the GICR_VPENDBASER.Dirty bit
In order to reduce the impact of the VPT parsing happening on the GIC,
we can split the vcpu reseidency in two phases:
- programming GICR_VPENDBASER: this still happens in vcpu_load()
- checking for the VPT parsing to be complete: this can happen
on vcpu entry (in kvm_vgic_flush_hwstate())
This allows the GIC and the CPU to work in parallel, rewmoving some
of the entry overhead.
Suggested-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Shenming Lu <lushenming@huawei.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20201128141857.983-3-lushenming@huawei.com
Diffstat (limited to 'arch/arm64/kvm/vgic/vgic-v4.c')
| -rw-r--r-- | arch/arm64/kvm/vgic/vgic-v4.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm64/kvm/vgic/vgic-v4.c b/arch/arm64/kvm/vgic/vgic-v4.c index b5fa73c9fd35..66508b03094f 100644 --- a/arch/arm64/kvm/vgic/vgic-v4.c +++ b/arch/arm64/kvm/vgic/vgic-v4.c @@ -353,6 +353,18 @@ int vgic_v4_load(struct kvm_vcpu *vcpu) return err; } +void vgic_v4_commit(struct kvm_vcpu *vcpu) +{ + struct its_vpe *vpe = &vcpu->arch.vgic_cpu.vgic_v3.its_vpe; + + /* + * No need to wait for the vPE to be ready across a shallow guest + * exit, as only a vcpu_put will invalidate it. + */ + if (!vpe->ready) + its_commit_vpe(vpe); +} + static struct vgic_its *vgic_get_its(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *irq_entry) { |