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authorNeil Armstrong <narmstrong@baylibre.com>2020-03-13 10:07:13 +0100
committerKevin Hilman <khilman@baylibre.com>2020-03-17 15:15:09 -0700
commita084eaf3096c140deb4062fd09b6d20144d40ad7 (patch)
tree63da65d21aebc3ad3f2bc1610ceec60fc6d6132e /arch/arm64
parent0e1610e726d33f3bce1057470569acc96032a074 (diff)
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arm64: dts: meson-g12b-odroid-n2: add SPIFC controller node
Add disabled SPIFC controller node with instruction on how to enable it while lowering capabilities of the eMMC controller from 8bits bus width to 4bits bus width, it's data pins 4 to 7 being shared with the SPI NOR controller pins. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20200313090713.15147-5-narmstrong@baylibre.com
Diffstat (limited to 'arch/arm64')
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts21
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts
index b59ae1a297f2..169ea283d4ee 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts
@@ -451,6 +451,27 @@
vqmmc-supply = <&flash_1v8>;
};
+/*
+ * EMMC_D4, EMMC_D5, EMMC_D6 and EMMC_D7 pins are shared between SPI NOR pins
+ * and eMMC Data 4 to 7 pins.
+ * Replace emmc_data_8b_pins to emmc_data_4b_pins from sd_emmc_c pinctrl-0,
+ * and change bus-width to 4 then spifc can be enabled.
+ * The SW1 slide should also be set to the correct position.
+ */
+&spifc {
+ status = "disabled";
+ pinctrl-0 = <&nor_pins>;
+ pinctrl-names = "default";
+
+ mx25u64: spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mxicy,mx25u6435f", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <104000000>;
+ };
+};
+
&tdmif_b {
status = "okay";
};