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author | Jianguo Chen <chenjianguo3@huawei.com> | 2019-03-20 18:54:21 +0000 |
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committer | Marc Zyngier <marc.zyngier@arm.com> | 2019-03-21 11:08:26 +0000 |
commit | fca269f201a8d9985c0a31fb60b15d4eb57cef80 (patch) | |
tree | 7e7441a8d917b4bb087ca1012749e38ba0899239 /arch/arm | |
parent | 6a77623d78b307b34d4cf7886da6a907689bf388 (diff) | |
download | linux-fca269f201a8d9985c0a31fb60b15d4eb57cef80.tar.gz linux-fca269f201a8d9985c0a31fb60b15d4eb57cef80.tar.bz2 linux-fca269f201a8d9985c0a31fb60b15d4eb57cef80.zip |
irqchip/mbigen: Don't clear eventid when freeing an MSI
mbigen_write_msg clears eventid bits of a mbigen register
when free a interrupt, because msi_domain_deactivate memset
struct msg to zero. Then multiple mbigen pins with zero eventid
will report the same interrupt number.
The eventid clear call trace:
free_irq
__free_irq
irq_shutdown
irq_domain_deactivate_irq
__irq_domain_deactivate_irq
__irq_domain_deactivate_irq
msi_domain_deactivate
platform_msi_write_msg
mbigen_write_msg
Signed-off-by: Jianguo Chen <chenjianguo3@huawei.com>
[maz: massaged subject]
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'arch/arm')
0 files changed, 0 insertions, 0 deletions